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SY100S307JZ PDF预览

SY100S307JZ

更新时间: 2024-11-11 20:33:27
品牌 Logo 应用领域
美国微芯 - MICROCHIP 输入元件逻辑集成电路石英晶振
页数 文件大小 规格书
4页 337K
描述
100S SERIES, 5 2-INPUT XOR/XNOR GATE, PQCC28

SY100S307JZ 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:LEAD FREE, PLASTIC, LCC-28Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.71
系列:100SJESD-30 代码:S-PQCC-J28
JESD-609代码:e3长度:11.48 mm
逻辑集成电路类型:XOR/XNOR GATE湿度敏感等级:2
功能数量:5输入次数:2
端子数量:28最高工作温度:85 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):245
传播延迟(tpd):1 ns认证状态:Not Qualified
座面最大高度:4.57 mm表面贴装:YES
技术:ECL温度等级:OTHER
端子面层:MATTE TIN端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:11.48 mm
Base Number Matches:1

SY100S307JZ 数据手册

 浏览型号SY100S307JZ的Datasheet PDF文件第2页浏览型号SY100S307JZ的Datasheet PDF文件第3页浏览型号SY100S307JZ的Datasheet PDF文件第4页 
7  
SY100S307  
QUINTꢀEXCLUSIVE  
OR/NORꢀGATE  
FEATURES  
DESCRIPTION  
The SY100S307 is an ultra-fast quint exclusive-OR/NOR  
gate designed for use in high-performance ECL systems. A  
function output that is the wire-OR result of the exclusive-OR  
outputs is also available. The inputs on the device have 75kΩ  
pull-down resistors.  
■ꢀ Max.ꢀpropagationꢀdelayꢀofꢀ1000ps  
■ꢀ IEEꢀmin.ꢀofꢀ–58mA  
■ꢀ Extendedꢀsupplyꢀvoltageꢀoption:  
VEEꢀ=ꢀ–4.2Vꢀtoꢀ–5.5V  
■ꢀ Voltageꢀandꢀtemperatureꢀcompensationꢀforꢀimprovedꢀ  
noiseꢀimmunity  
■ꢀ Internalꢀ75kΩꢀinputꢀpull-downꢀresistors  
■ꢀ 50%ꢀfasterꢀthanꢀFairchildꢀ300Kꢀatꢀlowerꢀpower  
■ꢀ FunctionꢀandꢀpinoutꢀcompatibleꢀwithꢀFairchildꢀF100K  
■ꢀ Availableꢀinꢀ28-pinꢀPLCCꢀpackage  
ꢁLOCKꢀDIAGRAM  
PINꢀNAMES  
Pinꢀ  
Dna – Dne  
E
Function  
Data Inputs (n-1...5)  
Enable Input  
Oa – Oe  
Oa – Oe  
VEES  
Data Outputs  
Complementary Data Outputs  
VEE Substrate  
VCCA  
VCCO for ECL Outputs  
Rev.: I  
Amendment: /0  
M9999-060910  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: June 2010  

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