SY100S314JZ

更新时间： 2024-11-11 04:50:11

品牌	Logo	应用领域
麦瑞 - MICREL		接口集成电路
页数	文件大小	规格书
6页	87K
描述
QUINT DIFFERENTIAL LINE RECEIVER

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SY100S314JZ 数据手册

SY100S314

Micrel, Inc.

QUINT DIFFERENTIAL

LINE RECEIVER

DESCRIPTION

FEATURES

The SY100S314 offers five differential line receivers

with emitter follower outputs, designed for use in high-

performance ECL systems. For single-ended operation,

the VBB reference voltage is available. In the single-ended

mode, the apparent input threshold of the true inputs is

30mV higher than the threshold of the complementary

inputs.

■ Max. propagation delay of 900ps

■ Differential outputs

■ IEE min. of –60mA

■ Extended supply voltage option:

VEE = –4.2V to –5.5V

■ Voltage and temperature compensation for improved

Common mode rejection of +1.0V is achieved through

the use of active current sources. If both the true and

complement inputs are at the same potential between VEE

and VCC, then the complementary outputs will take on a

logic HIGH state. Unlike the other members of the Synergy

300K family, the inputs on this device do not have pull-

down resistors.

noise immunity

■ VBB output for single-ended use

■ More than twice as fast as Fairchild

■ Function and pinout compatible with Fairchild F100K

■ Available in 24-pin CERPACK and 28-pin PLCC

packages

PIN NAMES

BLOCK DIAGRAM

Da – De

Oa – Oe

VEES

Function

Data Inputs

Inverting Data Inputs

Data Outputs

Complementary Data Outputs

VEE Substrate

VCCA

VCCO for ECL Outputs

Rev.: H

Amendment:/0

M9999-032206

hbwhelp@micrel.com or (408) 955-1690

Issue Date: March 2006

12 3 4 5 6

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