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SY100S318JC PDF预览

SY100S318JC

更新时间: 2024-11-10 22:09:19
品牌 Logo 应用领域
麦瑞 - MICREL 栅极触发器逻辑集成电路
页数 文件大小 规格书
5页 99K
描述
5-WIDE 5, 4, 4, 4, 2 OA/OAI GATE

SY100S318JC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:PLASTIC, LCC-28Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.79
Is Samacsys:N系列:100S
JESD-30 代码:S-PQCC-J28JESD-609代码:e0
长度:11.48 mm逻辑集成电路类型:OR-AND/OR-AND-INVERT GATE
湿度敏感等级:1功能数量:1
输入次数:19端子数量:28
最高工作温度:85 °C最低工作温度:
输出特性:OPEN-EMITTER封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC28,.5SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):240电源:-4.5 V
最大电源电流(ICC):55 mAProp。Delay @ Nom-Sup:0.8 ns
传播延迟(tpd):0.8 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:4.57 mm
子类别:Gates表面贴装:YES
技术:ECL温度等级:COMMERCIAL EXTENDED
端子面层:Tin/Lead (Sn85Pb15)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:11.48 mm
Base Number Matches:1

SY100S318JC 数据手册

 浏览型号SY100S318JC的Datasheet PDF文件第2页浏览型号SY100S318JC的Datasheet PDF文件第3页浏览型号SY100S318JC的Datasheet PDF文件第4页浏览型号SY100S318JC的Datasheet PDF文件第5页 
5-WIDE 5, 4, 4, 4, 2  
OA/OAI GATE  
SY100S318  
DESCRIPTION  
FEATURES  
Max. propagation delay of 800ps  
IEE min. of –55mA  
The SY100S318 is an ultra-fast 5-wide 5, 4, 4, 4, 2 OR/  
AND gate with both true and complementary outputs,  
designed for use in high-performance ECL systems. The  
inputs on this device have 75Kpull-down resistors.  
Extended supply voltage option:  
VEE = –4.2V to –5.5V  
Voltage and temperature compensation for  
PIN CONFIGURATIONS  
improved noise immunity  
Internal 75Kinput pull-down resistors  
70% faster than Fairchild  
40% lower power than Fairchild  
11 10 9  
8 7 6 5  
Function and pinout compatible with Fairchild F100K  
D2b  
D3b  
12  
13  
14  
15  
16  
17  
18  
4
3
O
Available in 24-pin CERPACK and 28-pin PLCC  
O
packages  
VEE  
VEES  
D4b  
2
VCCA  
VCC  
VCC  
D2e  
D1e  
Top View  
PLCC  
J28-1  
1
28  
27  
26  
D1c  
D2c  
19 20 21 22 23 24 25  
BLOCK DIAGRAM  
D
D
D
D
D
1a  
2a  
3a  
4a  
5a  
24 23 22 21 20 19  
1
2
3
4
5
6
18  
17  
16  
15  
14  
13  
D
D
D
D
3c  
4c  
1d  
2d  
D
D
D
D
D
D
1b  
5a  
4a  
3a  
2a  
1a  
Top View  
Flatpack  
F24-1  
D
D
D
D
1b  
2b  
3b  
4b  
D
3d  
4d  
D
7
8 9 10 11 12  
D
D
D
D
1c  
2c  
3c  
4c  
O
O
D
D
D
D
1d  
2d  
3d  
4d  
PIN NAMES  
Pin  
Dna – Dne  
O – O  
Function  
D
D
1e  
2e  
Data Inputs (n = 1...5)  
Data Outputs  
VEES  
VEE Substrate  
VCCA  
VCCO for ECL Outputs  
Rev.: G  
Amendment:/0  
Issue Date: July, 1999  
1

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