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SY100S321_06 PDF预览

SY100S321_06

更新时间: 2024-11-11 05:04:27
品牌 Logo 应用领域
麦瑞 - MICREL /
页数 文件大小 规格书
6页 87K
描述
LOW-POWER 9-BIT INVERTER

SY100S321_06 数据手册

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LOW-POWER9-BIT  
INVERTER  
SY100S321  
FEATURES  
DESCRIPTION  
The SY100S321 is a monolithic 9-bit inverter. The device  
contains nine inverting buffer gates with single input and  
output.  
Max. propagation delay of 700ps  
IEE min. of –55mA  
Extended supply voltage option:  
VEE = –4.2V to –5.5V  
Voltage and temperature compensation for  
improved noise immunity  
70% faster than Fairchild 300K at lower power  
Internal 75Kinput pull-down resistors  
Function and pinout compatible with Fairchild F100K  
Available in 24-pin CERPACK and 28-pin PLCC  
packages  
PIN NAMES  
BLOCK DIAGRAM  
Pin  
D1 – D9  
Q1 – Q9  
VEES  
Function  
Data Inputs  
D
D
D
D
D
D
D
D
D
1
2
3
4
5
6
7
8
9
O
O
O
O
O
O
O
O
O
1
2
3
4
5
6
7
8
9
Data Outputs  
VEE Substrate  
VCCA  
VCCO for ECL Outputs  
Rev.: H  
Amendment:/0  
M9999-032206  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: March 2006  

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