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SY100S324 PDF预览

SY100S324

更新时间: 2024-11-10 22:59:23
品牌 Logo 应用领域
麦瑞 - MICREL 转换器
页数 文件大小 规格书
5页 106K
描述
LOW POWER HEX TTL-to-ECL TRANSLATOR

SY100S324 数据手册

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LOW POWER HEX  
TTL-to-ECL  
SY100S324  
TRANSLATOR  
FEATURES  
DESCRIPTION  
Max. propagation delay of 1.4ns  
IEE min. of –70mA  
The SY100S324 is a hex translator designed to convert  
TTL logic levels to 100K ECL levels. The inputs are TTL  
compatible with differential outputs that can either be  
used as an inverting/non-inverting translator or as  
differential line drivers. A common Enable (E), when LOW,  
holds all inverting outputs HIGH and holds all non-  
inverting outputs LOW.  
Industry standard 100K ECL levels  
Extended supply voltage option:  
VEE = –4.2V to –5.5V  
Differential outputs  
When used in the differential mode, due to its high  
common mode rejection, it overcomes voltage gradients  
between the TTL and ECL ground systems. The VEE and  
VTTL power may be applied in either order.  
Voltage and temperature compensation for improved  
noise immunity  
Internal 75Kinput pull-down resistors  
Twice as fast as Fairchild’s 324  
Function and pinout compatible with Fairchild F100K  
PIN CONFIGURATIONS  
Available in 24-pin CERPACK and 28-pin PLCC  
packages  
25  
24 23 22 21 20 19  
Q
Q
2
2
26  
27  
28  
1
18  
17  
16  
15  
14  
13  
12  
D
0
V
E
V
V
TTL  
V
CC  
CC  
Top View  
PLCC  
J28-1  
V
EES  
EE  
BLOCK DIAGRAM  
V
CCA  
CCA  
2
V
3
D
D
3
4
E
Q
3
4
5
6
7
8
9
10 11  
Q
Q
0
0
D
D
D
D
D
D
0
1
2
3
4
5
Q
Q
1
1
24 23 22 21 20 19  
D
D
Q
1
2
0
1
18  
17  
16  
D
5
2
3
Q
Q
5
5
Q
Q
2
2
Top View  
Flatpack  
F24-1  
Q
Q
Q
0
1
1
4
5
6
15  
14  
13  
Q
Q
Q
4
4
3
Q
Q
3
3
7
8
9
10 11 12  
Q
Q
4
4
Q
Q
5
5
PIN NAMES  
Pin  
Function  
D0–D5  
E
Data Inputs  
Enable Inputs  
Q0–Q5  
Q0–Q5  
VEES  
VTTL  
Data Outputs  
Complementary Data Outputs  
VEE Substrate  
TTL VCC Power Supply  
VCCO for ECL Outputs  
VCCA  
Rev.: F  
Amendment:/0  
Issue Date: July, 1999  
1

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