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SY100S324JYTR PDF预览

SY100S324JYTR

更新时间: 2024-11-11 03:01:51
品牌 Logo 应用领域
麦瑞 - MICREL 转换器锁存器接口集成电路
页数 文件大小 规格书
6页 506K
描述
LOW POWER HEX TTL-to-ECL TRANSLATOR

SY100S324JYTR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:QLCC
包装说明:QCCJ,针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.63
最大延迟:1.4 ns接口集成电路类型:TTL TO ECL TRANSLATOR
JESD-30 代码:S-PQCC-J28JESD-609代码:e3
长度:11.48 mm湿度敏感等级:2
位数:1功能数量:6
端子数量:28输出锁存器或寄存器:NONE
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:4.57 mm
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:ECL端子面层:Matte Tin (Sn)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:11.48 mmBase Number Matches:1

SY100S324JYTR 数据手册

 浏览型号SY100S324JYTR的Datasheet PDF文件第2页浏览型号SY100S324JYTR的Datasheet PDF文件第3页浏览型号SY100S324JYTR的Datasheet PDF文件第4页浏览型号SY100S324JYTR的Datasheet PDF文件第5页浏览型号SY100S324JYTR的Datasheet PDF文件第6页 
LOW POWER HEX  
TTL-to-ECL  
TRANSLATOR  
4  
SY100S324  
DESCRIPTION  
FEATURES  
Max. propagation delay of 1.4ns  
IEE min. of –70mA  
The SY100S324 is a hex translator designed to convert  
TTL logic levels to 100K ECL levels. The inputs are TTL  
compatible with differential outputs that can either be  
used as an inverting/non-inverting translator or as  
differential line drivers. A common Enable (E), when LOW,  
holds all inverting outputs HIGH and holds all non-  
inverting outputs LOW.  
Industry standard 100K ECL levels  
Extended supply voltage option:  
VEE = –4.2V to –5.5V  
Differential outputs  
When used in the differential mode, due to its high  
common mode rejection, it overcomes voltage gradients  
between the TTL and ECL ground systems. The VEE and  
VTTL power may be applied in either order.  
Voltage and temperature compensation for improved  
noise immunity  
Internal 75Kinput pull-down resistors  
Twice as fast as Fairchild’s 324  
Function and pinout compatible with Fairchild F100K  
Available in 24-pin CERPACK and 28-pin PLCC  
packages  
BLOCK DIAGRAM  
PIN NAMES  
E
Pin  
D0–D5  
Function  
Data Inputs  
Q
Q
0
0
D
D
D
D
D
D
0
1
2
3
4
5
E
Enable Inputs  
Q
Q
1
1
Q0–Q5  
Q0–Q5  
VEES  
VTTL  
VCCA  
Data Outputs  
Complementary Data Outputs  
VEE Substrate  
Q
Q
2
2
TTL VCC Power Supply  
VCCO for ECL Outputs  
Q
Q
3
3
Q
Q
4
4
Q
Q
5
5
Rev.: H  
Amendment:/0  
M9999-061306  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: June 2006  

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