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SY100S321JC PDF预览

SY100S321JC

更新时间: 2024-11-10 22:36:07
品牌 Logo 应用领域
麦瑞 - MICREL 栅极触发器逻辑集成电路
页数 文件大小 规格书
5页 102K
描述
LOW-POWER 9-BIT INVERTER

SY100S321JC 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:PLASTIC, LCC-28Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.44
Is Samacsys:N系列:100S
JESD-30 代码:S-PQCC-J28JESD-609代码:e0
逻辑集成电路类型:INVERTER功能数量:9
输入次数:1端子数量:28
最高工作温度:85 °C最低工作温度:
输出特性:OPEN-EMITTER封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC28,.5SQ
封装形状:SQUARE封装形式:CHIP CARRIER
电源:-4.5 V最大电源电流(ICC):55 mA
Prop。Delay @ Nom-Sup:0.7 ns传播延迟(tpd):0.7 ns
认证状态:Not Qualified施密特触发器:NO
子类别:Gates表面贴装:YES
技术:ECL温度等级:OTHER
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
Base Number Matches:1

SY100S321JC 数据手册

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LOW-POWER 9-BIT  
INVERTER  
SY100S321  
FEATURES  
DESCRIPTION  
The SY100S321 is a monolithic 9-bit inverter. The device  
contains nine inverting buffer gates with single input and  
output.  
Max. propagation delay of 700ps  
IEE min. of –55mA  
Extended supply voltage option:  
VEE = –4.2V to –5.5V  
Voltage and temperature compensation for  
improved noise immunity  
PIN CONFIGURATIONS  
70% faster than Fairchild 300K at lower power  
Internal 75Kinput pull-down resistors  
Function and pinout compatible with Fairchild F100K  
Available in 24-pin CERPACK and 28-pin PLCC  
11 10 9  
8 7 6 5  
packages  
D6  
D7  
12  
13  
14  
15  
16  
17  
18  
4
3
O7  
O8  
VEE  
VEES  
VCCA  
D8  
Top View  
PLCC  
2
VCCA  
VCC  
VCC  
O9  
1
J28-1  
28  
27  
26  
D9  
O1  
BLOCK DIAGRAM  
19 20 21 22 23 24 25  
D
D
D
D
D
D
D
D
D
1
2
3
4
5
6
7
8
9
O
O
O
O
O
O
O
O
O
1
2
3
4
5
6
7
8
9
24 23 22 21 20 19  
D
D
D
1
2
3
1
2
3
4
5
6
18  
D
D
5
4
17  
16  
15  
14  
13  
Top View  
Flatpack  
F24-1  
VCCA  
V
CCA  
Q
Q
Q
4
5
6
O
O
3
2
7
8 9 10 11 12  
PIN NAMES  
Pin  
D1 – D9  
Q1 – Q9  
VEES  
Function  
Data Inputs  
Data Outputs  
VEE Substrate  
VCCO for ECL Outputs  
VCCA  
Rev.: G  
Amendment:/0  
Issue Date: July, 1999  
1

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