Datasheet > SY100S317_07

SY100S317_07

更新时间： 2024-11-11 07:20:07

品牌	Logo	应用领域
麦瑞 - MICREL		/
页数	文件大小	规格书
4页	79K
描述
TRIPLE 2-WIDE OA/OAI GATE

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中文翻译

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数据手册

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SY100S317_07 数据手册

SY100S317

Micrel, Inc.

TRIPLE 2-WIDE

OA/OAIGATE

FEATURES

DESCRIPTION

The SY100S317 is a set of ultra-fast, triple 2-wide OR/

AND gates designed for use in high-performance ECL

systems. This device offers both true and complement

outputs. The inputs on this device have 75kΩ pull-down

resistors.

■ Max. propagation delay of 900ps

■ IEE min. of –48mA

■ Extended supply voltage option:

VEE = –4.2V to –5.5V

■ Voltage and temperature compensation for improved

noise immunity

■ Internal 75kΩ input pull-down resistors

■ Approximately 40% lower power than Fairchild

■ Function and pinout compatible with Fairchild F100K

■ Available in 28-pin PLCC package

BLOCK DIAGRAM

PIN NAMES

Dna – Dnc

Ea – Ec

Oa – Oc

VEES

Function

Data Inputs (n = 1...4)

Enable Inputs

Data Outputs

Complementary Data Outputs

VEE Substrate

VCCA

VCCO for ECL Outputs

Rev.: I

Amendment:/0

M9999-042307

hbwhelp@micrel.com or (408) 955-1690

Issue Date: April 2007

12 3 4

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