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SY100S302JZTR PDF预览

SY100S302JZTR

更新时间: 2024-11-24 07:20:11
品牌 Logo 应用领域
麦瑞 - MICREL 栅极逻辑集成电路输入元件
页数 文件大小 规格书
4页 79K
描述
QUINT 2-INPUT OR/NOR GATE

SY100S302JZTR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QLCC
包装说明:QCCJ,针数:28
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.71Is Samacsys:N
系列:100SJESD-30 代码:S-PQCC-J28
JESD-609代码:e3长度:11.48 mm
逻辑集成电路类型:OR/NOR GATE湿度敏感等级:2
功能数量:5输入次数:2
端子数量:28最高工作温度:85 °C
最低工作温度:输出特性:OPEN-EMITTER
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):260传播延迟(tpd):0.7 ns
认证状态:Not Qualified座面最大高度:4.57 mm
表面贴装:YES技术:ECL
温度等级:COMMERCIAL EXTENDED端子面层:Matte Tin (Sn)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:11.48 mmBase Number Matches:1

SY100S302JZTR 数据手册

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SY100S302  
QUINT 2-INPUT  
OR/NOR GATE  
FEATURES  
DESCRIPTION  
Max. propagation delay of 700ps  
IEE min. of –45mA  
The SY100S302 offers five 2-input OR/NOR gates  
designed for use in high-performance ECL systems. The  
five gates are controlled by a common Enable signal. All  
inputs have 75kpull-down resistors and all outputs are  
buffered.  
Industry standard 100K ECL levels  
Extended supply voltage option:  
VEE = –4.2V to –5.5V  
Voltage and temperature compensation for  
improved noise immunity  
Internal 75kinput pull-down resistors  
50% faster than Fairchild 300K  
Function and pinout compatible with Fairchild F100K  
Available in 28-pin PLCC package  
BLOCK DIAGRAM  
PIN NAMES  
Pin  
Dna – Dne  
E
Function  
Data Inputs (n-1...5)  
D
D
1a  
2a  
O
O
a
a
Enable Input  
Oa – Oe  
Oa – Oe  
VEES  
Data Outputs  
D
D
1b  
2b  
O
O
b
b
Complementary Data Outputs  
VEE Substrate  
VCCA  
VCCO for ECL Outputs  
D
D
1c  
2c  
O
O
c
c
D
D
1d  
2d  
O
O
d
d
D
D
1e  
2e  
O
O
e
e
E
Rev.: I  
Amendment:/0  
M9999-042307  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: April 2007  

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