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SY100S302JZ PDF预览

SY100S302JZ

更新时间: 2024-11-24 07:20:11
品牌 Logo 应用领域
麦瑞 - MICREL 输入元件
页数 文件大小 规格书
4页 79K
描述
QUINT 2-INPUT OR/NOR GATE

SY100S302JZ 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QLCC
包装说明:QCCJ, LDCC28,.5SQ针数:28
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.71系列:100S
JESD-30 代码:S-PQCC-J28JESD-609代码:e3
长度:11.48 mm逻辑集成电路类型:OR/NOR GATE
湿度敏感等级:2功能数量:5
输入次数:2端子数量:28
最高工作温度:85 °C最低工作温度:
输出特性:OPEN-EMITTER封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC28,.5SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):260电源:-4.5 V
最大电源电流(ICC):45 mAProp。Delay @ Nom-Sup:0.7 ns
传播延迟(tpd):0.7 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:4.57 mm
子类别:Gates表面贴装:YES
技术:ECL温度等级:COMMERCIAL EXTENDED
端子面层:Matte Tin (Sn)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:11.48 mm
Base Number Matches:1

SY100S302JZ 数据手册

 浏览型号SY100S302JZ的Datasheet PDF文件第2页浏览型号SY100S302JZ的Datasheet PDF文件第3页浏览型号SY100S302JZ的Datasheet PDF文件第4页 
SY100S302  
QUINT 2-INPUT  
OR/NOR GATE  
FEATURES  
DESCRIPTION  
Max. propagation delay of 700ps  
IEE min. of –45mA  
The SY100S302 offers five 2-input OR/NOR gates  
designed for use in high-performance ECL systems. The  
five gates are controlled by a common Enable signal. All  
inputs have 75kpull-down resistors and all outputs are  
buffered.  
Industry standard 100K ECL levels  
Extended supply voltage option:  
VEE = –4.2V to –5.5V  
Voltage and temperature compensation for  
improved noise immunity  
Internal 75kinput pull-down resistors  
50% faster than Fairchild 300K  
Function and pinout compatible with Fairchild F100K  
Available in 28-pin PLCC package  
BLOCK DIAGRAM  
PIN NAMES  
Pin  
Dna – Dne  
E
Function  
Data Inputs (n-1...5)  
D
D
1a  
2a  
O
O
a
a
Enable Input  
Oa – Oe  
Oa – Oe  
VEES  
Data Outputs  
D
D
1b  
2b  
O
O
b
b
Complementary Data Outputs  
VEE Substrate  
VCCA  
VCCO for ECL Outputs  
D
D
1c  
2c  
O
O
c
c
D
D
1d  
2d  
O
O
d
d
D
D
1e  
2e  
O
O
e
e
E
Rev.: I  
Amendment:/0  
M9999-042307  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: April 2007  

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