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SY100S302JCTR PDF预览

SY100S302JCTR

更新时间: 2024-11-26 22:33:07
品牌 Logo 应用领域
麦瑞 - MICREL 输入元件
页数 文件大小 规格书
5页 100K
描述
QUINT 2-INPUT OR/NOR GATE

SY100S302JCTR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:PLASTIC, LCC-28Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.77
系列:100SJESD-30 代码:S-PQCC-J28
JESD-609代码:e0长度:11.48 mm
逻辑集成电路类型:OR/NOR GATE湿度敏感等级:1
功能数量:5输入次数:2
端子数量:28最高工作温度:85 °C
最低工作温度:输出特性:OPEN-EMITTER
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC28,.5SQ封装形状:SQUARE
封装形式:CHIP CARRIER包装方法:TAPE AND REEL
峰值回流温度(摄氏度):240电源:-4.5 V
最大电源电流(ICC):45 mAProp。Delay @ Nom-Sup:0.7 ns
传播延迟(tpd):0.7 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:4.57 mm
子类别:Gates表面贴装:YES
技术:ECL温度等级:COMMERCIAL EXTENDED
端子面层:Tin/Lead (Sn85Pb15)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:11.48 mm
Base Number Matches:1

SY100S302JCTR 数据手册

 浏览型号SY100S302JCTR的Datasheet PDF文件第2页浏览型号SY100S302JCTR的Datasheet PDF文件第3页浏览型号SY100S302JCTR的Datasheet PDF文件第4页浏览型号SY100S302JCTR的Datasheet PDF文件第5页 
QUINT 2-INPUT  
OR/NOR GATE  
SY100S302  
FEATURES  
DESCRIPTION  
Max. propagation delay of 700ps  
IEE min. of –45mA  
The SY100S302 offers five 2-input OR/NOR gates  
designed for use in high-performance ECL systems. The  
five gates are controlled by a common Enable signal. All  
inputs have 75Kpull-down resistors and all outputs are  
buffered.  
Industry standard 100K ECL levels  
Extended supply voltage option:  
VEE = –4.2V to –5.5V  
Voltage and temperature compensation for  
PIN CONFIGURATIONS  
improved noise immunity  
Internal 75Kinput pull-down resistors  
50% faster than Fairchild 300K  
Function and pinout compatible with Fairchild F100K  
11 10 9  
8 7 6 5  
D1b  
D2b  
VEE  
VEES  
E
12  
13  
14  
15  
16  
17  
18  
4
3
Oc  
Available in 24-pin CERPACK and 28-pin PLCC  
Oc  
packages  
Top View  
PLCC  
J28-1  
2
VCCA  
VCC  
VCC  
Od  
1
28  
27  
26  
D1c  
D2c  
Od  
19 20 21 22 23 24 25  
BLOCK DIAGRAM  
D
D
1a  
2a  
O
O
a
a
24 23 22 21 20 19  
1
2
3
4
5
6
18  
17  
16  
15  
14  
13  
D
D
1d  
2d  
D
D
2a  
1a  
D
D
1b  
2b  
O
O
b
b
Top View  
Flatpack  
F24-1  
D
D
1e  
2e  
O
O
O
O
a
a
b
b
O
e
O
e
D
D
1c  
2c  
O
O
c
c
7
8 9 10 11 12  
D
D
1d  
2d  
O
O
d
d
D
D
1e  
2e  
O
O
e
e
PIN NAMES  
Pin  
Dna – Dne  
E
Function  
E
Data Inputs (n-1...5)  
Enable Input  
Oa – Oe  
Oa – Oe  
VEES  
Data Outputs  
Complementary Data Outputs  
VEE Substrate  
VCCA  
VCCO for ECL Outputs  
Rev.: G  
Amendment:/0  
Issue Date: July, 1999  
1

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