SSTU32864EC/G

更新时间： 2024-11-05 06:14:23

品牌	Logo	应用领域
恩智浦 - NXP		逻辑集成电路驱动双倍数据速率
页数	文件大小	规格书
21页	116K
描述
1.8 V configurable registered buffer for DDR2 RDIMM applications

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技术参数
数据手册
替代型号

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SSTU32864EC/G 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	LFBGA, BGA96,6X16,32
针数：	96	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.33
其他特性：	14 BIT 1:2 CONFIGURATION ALSO POSSIBLE	系列：	SSTU
JESD-30 代码：	R-PBGA-B96	JESD-609代码：	e1
长度：	13.5 mm	逻辑集成电路类型：	D FLIP-FLOP
湿度敏感等级：	2	位数：	25
功能数量：	1	端子数量：	96
最高工作温度：	70 °C	最低工作温度：
输出极性：	TRUE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFBGA	封装等效代码：	BGA96,6X16,32
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	260	电源：	1.8 V
传播延迟（tpd）：	2 ns	认证状态：	Not Qualified
座面最大高度：	1.5 mm	子类别：	Other Logic ICs
最大供电电压 (Vsup)：	1.9 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	TIN SILVER COPPER	端子形式：	BALL
端子节距：	0.8 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	30	触发器类型：	POSITIVE EDGE
宽度：	5.5 mm	最小 fmax：	450 MHz
Base Number Matches：	1

SSTU32864EC/G 数据手册

SSTU32864

1.8 V conﬁgurable registered buffer for DDR2 RDIMM

applications

Rev. 02 — 22 October 2004

Product data sheet

1. General description

The SSTU32864 is a 25-bit 1:1 or 14-bit 1:2 conﬁgurable registered buffer designed for

1.7 V to 1.9 V V_DDoperation.

All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The

control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized

to drive the DDR2 DIMM load.

The SSTU32864 operates from a differential clock (CK and CK). Data are registered at

the crossing of CK going HIGH, and CK going LOW.

The C0 input controls the pinout conﬁguration of the 1:2 pinout from A conﬁguration (when

LOW) to B conﬁguration (when HIGH). The C1 input controls the pinout conﬁguration from

25-bit 1:1 (when LOW) to 14-bit 1:2 (when HIGH).

The device supports low-power standby operation. When the reset input (RESET) is LOW,

the differential input receivers are disabled, and undriven (ﬂoating) data, clock and

reference voltage (V_REF) inputs are allowed. In addition, when RESET is LOW all registers

are reset, and all outputs are forced LOW. The LVCMOS RESET and Cn inputs must

always be held at a valid logic HIGH or LOW level.

To ensure deﬁned outputs from the register before a stable clock has been supplied,

RESET must be held in the LOW state during power-up.

In the DDR2 RDIMM application, RESET is speciﬁed to be completely asynchronous with

respect to CK and CK. Therefore, no timing relationship can be guaranteed between the

two. When entering reset, the register will be cleared and the data outputs will be driven

LOW quickly, relative to the time to disable the differential input receivers. However, when

coming out of reset, the register will become active quickly, relative to the time to enable

the differential input receivers. As long as the data inputs are LOW, and the clock is stable

during the time from the LOW-to-HIGH transition of RESET until the input receivers are

fully enabled, the design of the SSTU32864 must ensure that the outputs will remain

LOW, thus ensuring no glitches on the output.

The device monitors both DCS and CSR inputs and will gate the Qn outputs from

changing states when both DCS and CSR inputs are HIGH. If either DCS or CSR input is

LOW, the Qn outputs will function normally. The RESET input has priority over the DCS

and CSR control and will force the outputs LOW. If the DCS-control functionality is not

desired, then the CSR input can be hardwired to ground, in which case the setup time

requirement for DCS would be the same as for the other Dn data inputs.

The SSTU32864 is available in a 96-ball, low proﬁle ﬁne-pitch ball grid array (LFBGA96)

package.

12 3 4 5 6 7...21

中文翻译

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SSTU32864EC/G 替代型号

型号	品牌	替代类型	描述	数据表
PI74SSTUA32864NBE	PERICOM	功能相似	25-Bit 1:1 or 14-Bit 1:2 Confi gurable Registered Buff er

与SSTU32864EC/G相关器件

型号	品牌	获取价格	描述	数据表
SSTU32864EC/G,518	NXP	获取价格	SSTU32864 - 1.8 V configurable registered buffer for DDR2 RDIMM applications BGA 96-Pin
SSTU32864HT	IDT	获取价格	Interface Circuit
SSTU32865	NXP	获取价格	1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM
SSTU32865EG	NXP	获取价格	1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM
SSTU32865ET	NXP	获取价格	1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM
SSTU32865ET,518	NXP	获取价格	SSTU32865 - 1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM applications BGA
SSTU32865ET,557	NXP	获取价格	SSTU32865 - 1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM applications BGA
SSTU32866	NXP	获取价格	1.8 V 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity for DDR2 RDIMM a
SSTU32866EC	NXP	获取价格	1.8 V 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity for DDR2 RDIMM a
SSTU32866EC/G	NXP	获取价格	1.8 V 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity for DDR2 RDIMM a

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