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SSTU32864HT PDF预览

SSTU32864HT

更新时间: 2024-11-06 04:29:43
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
11页 111K
描述
Interface Circuit

SSTU32864HT 数据手册

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ICSSSTU32864  
Integrated  
Circuit  
Systems,Inc.  
25-BitConfigurableRegisteredBuffer  
Pin Configuration  
Recommended Application:  
DDR2 Memory Modules  
1
2
3
4
5
6
Provides complete DDR DIMM logic solution with  
ICS97U877  
A
B
C
D
E
F
Product Features:  
25-bit 1:1 or 14-bit 1:2 configurable registered buffer  
Supports SSTL_18 JEDEC specification on data  
inputs and outputs  
Supports LVCMOS switching levels on CSR# and  
RESET# inputs  
Low voltage operation  
VDD = 1.7V to 1.9V  
G
H
J
K
L
Available in 96 BGA package  
M
N
P
R
T
96 Ball BGA  
(Top View)  
Truth Table  
Inputs  
Outputs  
QCS#  
Dn,  
DODT,  
DCKE  
QODT,  
QCKE  
RST#  
DCS#  
CSR#  
CK  
CK#  
Qn  
Ball Assignments  
H
H
H
H
H
H
H
H
H
H
H
H
L
H
X
L
L
L
L
L
L
L
L
L
L
DCKE  
D2  
NC  
VREF  
GND  
VDD  
GND  
VDD  
GND  
VDD  
GND  
VDD  
GND  
VDD  
GND  
VDD  
GND  
VDD  
VREF  
VDD  
GND  
VDD  
GND  
VDD  
GND  
VDD  
GND  
VDD  
GND  
VDD  
GND  
VDD  
GND  
VDD  
VDD  
QCKE  
NC  
H
H
A
B
C
D
E
F
Q
0
Q
0
Q
0
L or H  
L or H  
L or H  
L or H  
L or H  
L or H  
D15  
D16  
NC  
Q2  
Q15  
Q16  
NC  
L
L
L
L
L
L
H
H
H
L
L
D3  
Q3  
H
X
H
H
DODT  
D5  
QODT  
Q5  
Q
0
Q
0
Q
0
D17  
D18  
RST#  
DCS#  
CSR#  
D19  
D20  
D21  
D22  
D23  
D24  
D25  
Q17  
Q18  
C0  
L
L
L
H
H
H
L
L
L
H
H
H
X
H
H
D6  
Q6  
Q
0
Q
0
Q
0
NC  
C1  
G
H
J
Q
0
H
H
L
L
H
H
H
H
CK  
QCS#  
ZOH  
Q8  
NC  
Q
0
H
X
H
CK#  
D8  
ZOL  
Q19  
Q20  
Q21  
Q22  
Q23  
Q24  
Q25  
Q
0
Q
0
Q
0
H
H
L or H  
X or  
L or H  
X or  
X or  
X or  
X or  
K
L
L
L
L
L
Floating Floating Floating Floating Floating  
D9  
Q9  
D10  
D11  
D12  
D13  
D14  
Q10  
Q11  
Q12  
Q13  
Q14  
M
N
P
R
T
1
2
3
4
5
6
1:1 Register (C0 = 0, C1 = 0)  
0727C—04/15/04  

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