SSTUA32866

更新时间： 2024-02-24 01:50:46

品牌	Logo	应用领域
恩智浦 - NXP		双倍数据速率
页数	文件大小	规格书
27页	144K
描述
1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applications

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SSTUA32866 技术参数

是否Rohs认证：	符合	生命周期：	Transferred
包装说明：	FBGA, BGA96,6X16,32	Reach Compliance Code：	unknown
风险等级：	5.67	Is Samacsys：	N
JESD-30 代码：	R-PBGA-B96	逻辑集成电路类型：	BUS DRIVER
端子数量：	96	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	FBGA	封装等效代码：	BGA96,6X16,32
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, FINE PITCH
电源：	1.8 V	认证状态：	Not Qualified
子类别：	Other Logic ICs	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	BALL
端子节距：	0.8 mm	端子位置：	BOTTOM
Base Number Matches：	1

SSTUA32866 数据手册

SSTUA32866

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 conﬁgurable registered buffer

with parity for DDR2-667 RDIMM applications

Rev. 01 — 15 July 2005

Product data sheet

1. General description

The SSTUA32866 is a 1.8 V conﬁgurable register speciﬁcally designed for use on DDR2

memory modules requiring a parity checking function. It is deﬁned in accordance with the

JEDEC standard for the SSTUA32866 registered buffer. The register is conﬁgurable

(using conﬁguration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in

the latter conﬁguration can be designated as Register A or Register B on the DIMM.

The SSTUA32866 accepts a parity bit from the memory controller on its parity bit

(PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs

and indicates whether a parity error has occurred on its open-drain QERR pin

(active LOW). The convention is even parity, that is, valid parity is deﬁned as an even

number of ones across the DIMM-independent data inputs combined with the parity input

bit.

The SSTUA32866 is packaged in a 96-ball, 6 × 16 grid, 0.8 mm ball pitch LFBGA package

(13.5 mm × 5.5 mm).

2. Features

■ Conﬁgurable register supporting DDR2 up to 667 MT/s Registered DIMM applications

■ Conﬁgurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode

■ Controlled output impedance drivers enable optimal signal integrity and speed

■ Exceeds JESD82-7 speed performance (1.8 ns max. single-bit switching propagation

delay; 2.0 ns max. mass-switching)

■ Supports up to 450 MHz clock frequency of operation

■ Optimized pinout for high-density DDR2 module design

■ Chip-selects minimize power consumption by gating data outputs from changing state

■ Supports SSTL_18 data inputs

■ Checks parity on the DIMM-independent data inputs

■ Partial parity output and input allows cascading of two SSTUA32866s for correct parity

error processing

■ Differential clock (CK and CK) inputs

■ Supports LVCMOS switching levels on the control and RESET inputs

■ Single 1.8 V supply operation (1.7 V to 2.0 V)

■ Available in 96-ball, 13.5 × 5.5 mm, 0.8 mm ball pitch LFBGA package

3. Applications

■ 400 MT/s to 667 MT/s DDR2 registered DIMMs desiring parity checking functionality

12 3 4 5 6 7...27

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与SSTUA32866相关器件

型号	品牌	获取价格	描述	数据表
SSTUA32866BHLFT	IDT	获取价格	CABGA-96, Reel
SSTUA32866BHMLF-T	IDT	获取价格	Interface Circuit
SSTUA32866BHM-T	IDT	获取价格	Interface Circuit
SSTUA32866BH-T	IDT	获取价格	Interface Circuit
SSTUA32866EC	NXP	获取价格	1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667
SSTUA32866EC,518	NXP	获取价格	SSTUA32866 - 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity
SSTUA32866EC/G	NXP	获取价格	1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667
SSTUA32866EC/G,518	NXP	获取价格	SSTUA32866 - 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity
SSTUA32866EC/G,557	NXP	获取价格	SSTUA32866EC
SSTUA32866EC-G	NXP	获取价格	1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667

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