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SSTU32865ET,518 PDF预览

SSTU32865ET,518

更新时间: 2024-11-05 19:44:11
品牌 Logo 应用领域
恩智浦 - NXP 双倍数据速率逻辑集成电路触发器
页数 文件大小 规格书
29页 139K
描述
SSTU32865 - 1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM applications BGA 160-Pin

SSTU32865ET,518 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:TFBGA,针数:160
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.75系列:SSTU
JESD-30 代码:R-PBGA-B160长度:13 mm
逻辑集成电路类型:D FLIP-FLOP位数:28
功能数量:1端子数量:160
最高工作温度:70 °C最低工作温度:
输出特性:OPEN-DRAIN输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TFBGA
封装形状:RECTANGULAR封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH
传播延迟(tpd):2.15 ns认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES温度等级:COMMERCIAL
端子形式:BALL端子节距:0.65 mm
端子位置:BOTTOM触发器类型:POSITIVE EDGE
宽度:9 mm最小 fmax:270 MHz
Base Number Matches:1

SSTU32865ET,518 数据手册

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SSTU32865  
1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM  
applications  
Rev. 02 — 28 September 2004  
Product data sheet  
1. General description  
The SSTU32865 is a 1.8 V 28-bit 1:2 register specifically designed for use on two rank by  
four (2R × 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It is  
similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the  
functionality of the normally required two registers in a single package, thereby freeing up  
board real-estate and facilitating routing to accommodate high-density Dual In-line  
Memory Module (DIMM) designs.  
The SSTU32865 also integrates a parity function, which accepts a parity bit from the  
memory controller, compares it with the data received on the D-inputs and indicates  
whether a parity error has occurred on its open-drain PTYERR pin (active-LOW).  
The SSTU32865 is packaged in a 160-ball, 12 × 18 grid, 0.65 mm ball pitch, thin profile  
fine-pitch ball grid array (TFBGA) package, which—while requiring a minimum  
9 mm × 13 mm of board space—allows for adequate signal routing and escape using  
conventional card technology.  
2. Features  
28-bit data register supporting DDR2  
Fully compliant to JEDEC standard JESD82-9  
Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two  
JEDEC-standard DDR2 registers (i.e. 2 × SSTU32864 or 2 × SSTU32866)  
Parity checking function across 22 input data bits  
Parity out signal  
Controlled output impedance drivers enable optimal signal integrity and speed  
Exceeds JESD82-9 speed performance (1.8 ns max. single-bit switching propagation  
delay, 2.0 ns max. mass-switching)  
Supports up to 450 MHz clock frequency of operation  
Optimized pinout for high-density DDR2 module design  
Chip-selects minimize power consumption by gating data outputs from changing state  
Supports Stub Series Terminated Logic SSTL_18 data inputs  
Differential clock (CK and CK) inputs  
Supports Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS)  
switching levels on the control and RESET inputs  
Single 1.8 V supply operation  
Available in 160-ball 9 mm × 13 mm, 0.65 mm ball pitch TFBGA package  
 
 

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