Datasheet > SSTU32866

SSTU32866

更新时间： 2024-11-05 06:14:23

品牌	Logo	应用领域
恩智浦 - NXP		双倍数据速率
页数	文件大小	规格书
29页	153K
描述
1.8 V 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity for DDR2 RDIMM applications

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SSTU32866 数据手册

SSTU32866

1.8 V 25-bit 1:1 or 14-bit 1:2 conﬁgurable registered buffer

with parity for DDR2 RDIMM applications

Rev. 02 — 11 November 2004

Product data sheet

1. General description

The SSTU32866 is a 1.8 V conﬁgurable register speciﬁcally designed for use on DDR2

memory modules requiring a parity checking function. It is deﬁned in accordance with the

JEDEC JESD82-7 standard for the SSTU32864 registered buffer, while adding the parity

checking function in a compatible pinout. The JEDEC standard for SSTU32866 is pending

publication. The register is conﬁgurable (using conﬁguration pins C0 and C1) to two

topologies: 25-bit 1:1 or 14-bit 1:2, and in the latter conﬁguration can be designated as

The SSTU32866 accepts a parity bit from the memory controller on its parity bit (PAR_IN)

input, compares it with the data received on the DIMM-independent D-inputs and

indicates whether a parity error has occurred on its open-drain QERR pin (active-LOW).

The convention is even parity, that is, valid parity is deﬁned as an even number of ones

across the DIMM-independent data inputs combined with the parity input bit.

The SSTU32866 is packaged in a 96-ball, 6 × 16 grid, 0.8 mm ball pitch LFBGA package

(13.5 mm by 5.5 mm).

2. Features

■ Conﬁgurable register supporting DDR2 Registered DIMM applications

■ Conﬁgurable to 25-bit 1:1 mode or 14-bit 1:2 mode

■ Controlled output impedance drivers enable optimal signal integrity and speed

■ Exceeds JESD82-7 speed performance (1.8 ns max. single-bit switching propagation

delay; 2.0 ns max. mass-switching)

■ Supports up to 450 MHz clock frequency of operation

■ Optimized pinout for high-density DDR2 module design

■ Chip-selects minimize power consumption by gating data outputs from changing state

■ Supports SSTL_18 data inputs

■ Checks parity on the DIMM-independent data inputs

■ Partial parity output and input allows cascading of two SSTU32866s for correct parity

error processing

■ Differential clock (CK and CK) inputs

■ Supports LVCMOS switching levels on the control and RESET inputs

■ Single 1.8 V supply operation

■ Available in 96-ball, 13.5 × 5.5 mm, 0.8 mm ball pitch LFBGA package

12 3 4 5 6 7...29

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与SSTU32866相关器件

型号	品牌	获取价格	描述	数据表
SSTU32866EC	NXP	获取价格	1.8 V 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity for DDR2 RDIMM a
SSTU32866EC/G	NXP	获取价格	1.8 V 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity for DDR2 RDIMM a
SSTU32866EC/G,518	NXP	获取价格	SSTU32866 - 1.8 V 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity for
SSTU32866EC/G,551	NXP	获取价格	SSTU32866 - 1.8 V 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity for
SSTUA32864	NXP	获取价格	1.8 V configurable registered buffer for DDR2-667 RDIMM applications
SSTUA32864_07	NXP	获取价格	1.8 V configurable registered buffer for DDR2-667 RDIMM applications
SSTUA32864BHLF	IDT	获取价格	CABGA-96, Tray
SSTUA32864BHLF-T	IDT	获取价格	CABGA-96, Reel
SSTUA32864BHMLFT	IDT	获取价格	D Flip-Flop, SSTU Series, 1-Func, Positive Edge Triggered, 25-Bit, True Output, PBGA96, 5
SSTUA32864BHMLF-T	IDT	获取价格	D Flip-Flop, SSTU Series, 1-Func, Positive Edge Triggered, 25-Bit, True Output, PBGA96

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