Datasheet > SSM4567ACBZ-RL

SSM4567ACBZ-RL

更新时间： 2024-11-06 01:13:03

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
52页	968K
描述
Digital 2.5 W, 5.1 V, Boost Class-D Audio Amplifier with Output Sensing

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SSM4567ACBZ-RL 数据手册

Digital 2.5 W, 5.1 V, Boost Class-D Audio

Amplifier with Output Sensing

SSM4567

Data Sheet

Output noise: 21.7 μV rms, A-weighted

FEATURES

THD + N: 0.025% at 1 kHz, 500 mW output power

Filterless Class-D amplifier with spread-spectrum Σ-Δ

modulation with integrated boost regulator (5.1 V)

Digitized output of output voltage, output current, and VBAT

supply voltage

PSSR: 90 dB at 217 Hz, with dither input

72 dB signal-to-noise ratio (SNR) on output current sensing

and 77 dB SNR on voltage sensing

Quiescent power consumption: 19.8 mW

Pop-and-click suppression

Integrated boost regulator

Multiple serial data formats

PDM input/output

Flexible battery monitoring AGC

Short-circuit protection for boost and Class-D outputs and

thermal protection with automatic recovery

Smart power-down when PDM stop condition

or no clock input detected

DC blocking high-pass filter and static input DC protection

for PDM input

TDM slave with support for up to 8 chips on a single bus

I²S or left justified slave

Multichip I²S with support for up to 4 chips on one I²S bus

8 kHz to 192 kHz PCM sample rates

2.048 to 6.14 MHz PDM input sample rates

Configurable via I²C control, TDM control, or PDM patterns

Standalone control modes

Selectable ultralow EMI emissions and low latency modes

2.5 W into 4 Ω load and 1.42 W into 8 Ω load at 3.6 V supply

with <1% total harmonic distortion plus noise (THD + N)

Available in 19-ball, 1.74 mm × 2.1 mm, 0.4 mm pitch WLCSP

89.7% system efficiency into 8 Ω at 1 W, VBAT = 3.6 V

APPLICATIONS

Mobile handsets

Tablets

Portable media players

FUNCTIONAL BLOCK DIAGRAM

LR_SEL/

ADDR

SEL

BSTSW

BSTSW VBST VBST

SCL

SDA

SSM4567

BOOST (5V)

DAC_PDM_DAT/

DAC_SDATAI

Σ-∆

CLASS-D

MOD

FILTERING

MODULATION

H-BRIDGE

(5V)

OUTN

OUTP

DAC

DAC_PDM_CLK/

BCLK

I S/TDM/

PDM

INTERFACE

SNS_PDM_DAT/

SNS_SDATAO

PGND

ADC

SENSE

SNS_PDM_CLK/

FSYNC

ADC

SENSE

IOVDD

AGND

VBAT

Figure 1.

Rev. 0

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

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