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SN74LVTR245DW PDF预览

SN74LVTR245DW

更新时间: 2024-11-13 22:56:23
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件信息通信管理
页数 文件大小 规格书
7页 119K
描述
3.3-V ABT OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

SN74LVTR245DW 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP20,.4针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.51
其他特性:WITH DIRECTION CONTROL控制类型:COMMON CONTROL
计数方向:BIDIRECTIONAL系列:LVT
JESD-30 代码:R-PDSO-G20长度:12.8 mm
逻辑集成电路类型:BUS TRANSCEIVER最大I(ol):0.064 A
位数:4功能数量:2
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE电源:3.3 V
Prop。Delay @ Nom-Sup:4.6 ns传播延迟(tpd):5.8 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
翻译:N/A宽度:7.5 mm
Base Number Matches:1

SN74LVTR245DW 数据手册

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SN54LVTR245, SN74LVTR245  
3.3-V ABT OCTAL BUS TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCAS428 – OCTOBER 1993  
SN54LVTR245 . . . J PACKAGE  
SN74LVTR245 . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low-Static Power  
Dissipation  
DIR  
A1  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
Supports Mixed-Mode Signal Operation  
OE  
B1  
B2  
B3  
B4  
B5  
(5-V Input and Output Voltages With  
A2  
A3  
A4  
A5  
3.3-V V  
)
CC  
Supports Unregulated Battery Operation  
Down to 2.7 V  
Typical V  
(Output Ground Bounce)  
A6  
OLP  
< 0.8 V at V  
= 3.3 V, T = 25°C  
A7  
A8  
13 B6  
12 B7  
CC  
A
Latch-Up Performance Exceeds 500 mA  
11  
GND  
B8  
Per JEDEC Standard JESD-17  
Bus-Hold Data Inputs Eliminate the Need  
for External Pullup Resistors  
SN54LVTR245 . . . FK PACKAGE  
(TOP VIEW)  
Reduced Output Structure on A Port  
Minimizes V  
OHV  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK), and  
Ceramic DIPs (J)  
3
2
1
20 19  
18  
B1  
B2  
B3  
B4  
B5  
A3  
A4  
A5  
A6  
A7  
4
5
6
7
8
17  
16  
15  
14  
description  
9 10 11 12 13  
These octal bus transceivers are designed  
specifically for low-voltage (3.3-V) V operation,  
CC  
but with the capability to provide a TTL interface to  
a 5-V system environment.  
The LVTR245 is designed for asynchronous communication between data buses. The device transmits data  
from the A bus to the B bus or from the B bus to the A bus depending upon the logic level at the direction-control  
(DIR) input. The output-enable (OE) input can be used to disable the device so the buses are effectivelyisolated.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The A port is designed to minimize the undershoot exhibited on high to low transition during simultaneous  
switching conditions.  
The SN74LVTR245 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count  
and functionality of standard small-outline packages in less than half the printed-circuit-board area.  
The SN54LVTR245 is characterized for operation over the full military temperature range of 55°C to 125°C.  
The SN74LVTR245 is characterized for operation from 40°C to 85°C.  
FUNCTION TABLE  
INPUTS  
OPERATION  
OE  
L
DIR  
L
B data to A bus  
A data to B bus  
Isolation  
L
H
H
X
Copyright 1993, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74LVTR245DW 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVTR245NSR TI

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SN74LVTR245DWR TI

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