5秒后页面跳转
捷配首页

Datasheet > SN74LVTT244J
SN74LVTT244J PDF预览

SN74LVTT244J

更新时间： 2024-01-14 22:14:09
品牌 Logo 应用领域
德州仪器 - TI 驱动信息通信管理输出元件逻辑集成电路
页数 文件大小 规格书
7页 145K
描述
LVT SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, CDIP20, CERAMIC, DIP-20

阅读下载

中文翻译

获取价格

SN74LVTT244J 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP,针数：20
Reach Compliance Code：unknown风险等级：5.74
系列：LVTJESD-30 代码：R-GDIP-T20
长度：24.195 mm逻辑集成电路类型：BUS DRIVER
位数：4功能数量：2
端口数量：2端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
传播延迟（tpd）：5.2 ns认证状态：Not Qualified
座面最大高度：5.08 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：NO技术：BICMOS
温度等级：INDUSTRIAL端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
宽度：7.62 mmBase Number Matches：1

SN74LVTT244J 数据手册

 浏览型号SN74LVTT244J的Datasheet PDF文件第2页浏览型号SN74LVTT244J的Datasheet PDF文件第3页浏览型号SN74LVTT244J的Datasheet PDF文件第4页浏览型号SN74LVTT244J的Datasheet PDF文件第5页浏览型号SN74LVTT244J的Datasheet PDF文件第6页浏览型号SN74LVTT244J的Datasheet PDF文件第7页 
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢆ
ꢇ
ꢃ
ꢃ
ꢈ
ꢉ
ꢀ
ꢁ
ꢊ
ꢋ ꢌꢋ ꢍꢅ ꢉꢎꢏꢆ ꢉ ꢐꢑ ꢆꢎꢄꢉꢏ ꢒꢓ ꢓꢔ ꢕꢀ ꢖꢗ ꢕ ꢘꢅ ꢔ ꢕ  
ꢃ
ꢄ
ꢅ
ꢆ
ꢆ
ꢇ
ꢃ
ꢃ
ꢀ
ꢀ
ꢜ
ꢙ
ꢘ
ꢆ
ꢚ
ꢉ
ꢋ
ꢍ
ꢀ
ꢆ
ꢎ
ꢆ
ꢔ
ꢉ
ꢐ
ꢒ
ꢆ
ꢛ
ꢒ
ꢆ
SCES006 − FEBRUARY 1995  
SN54LVTT244 . . . J OR W PACKAGE  
SN74LVTT244 . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
• State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low-Static Power  
Dissipation  
1OE  
1A1  
2Y4  
1A2  
2Y3  
1A3  
2Y2  
1A4  
2Y1  
GND  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
• Support Mixed-Mode Signal Operation (5-V  
2OE  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
Input and Output Voltages With 3.3-V V  
)
CC  
• Support Unregulated Battery Operation  
Down to 2.7 V  
• Typical V  
(Output Ground Bounce)  
OLP  
< 0.8 V at V  
= 3.3 V, T = 25°C  
CC  
A
13 2A2  
12 1Y4  
• Latch-Up Performance Exceeds 500 mA  
Per JEDEC Standard JESD-17  
11  
2A1  
• Supports Live Insertion  
• Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK),  
Ceramic Flat (W) Packages, and Ceramic  
(J) DIPs  
SN54LVTT244 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
1A2  
2Y3  
1A3  
2Y2  
1A4  
4
5
6
7
8
description  
17  
16  
15  
14  
These octal buffers and line drivers are designed  
specifically for low-voltage (3.3-V) V operation,  
CC  
but with the capability to provide a TTL interface to  
a 5-V system environment.  
9 10 11 12 13  
The ’LVTT244 are organized as two 4-bit line  
drivers with separate output-enable (OE) inputs.  
When OE is low, the device passes data from the  
A inputs to the Y outputs. When OE is high, the  
outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
The SN74LVTT244 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count  
and functionality of standard small-outline packages in less than half the printed-circuit-board area.  
The SN54LVTT244 is characterized for operation over the full military temperature range of −55°C to 125°C.  
The SN74LVTT244 is characterized for operation from −40°C to 85°C.  
FUNCTION TABLE  
(each buffer)  
INPUTS  
OUTPUT  
Y
OE  
A
H
L
L
L
H
L
H
X
Z
Copyright 1995, Texas Instruments Incorporated  
ꢒ ꢁꢄ ꢔꢀꢀ ꢐ ꢆꢚ ꢔꢕꢙ ꢘꢀ ꢔ ꢁ ꢐꢆꢔ ꢗ ꢝꢞ ꢟꢠ ꢡꢢꢣ ꢤꢥ ꢦꢧꢝ ꢣꢢ ꢧꢝꢨ ꢟꢧꢠ ꢛꢕ ꢐ ꢗ ꢒ ꢑꢆ ꢘꢐ ꢁ  
ꢝ
ꢗ
ꢎ
ꢆ
ꢎ
ꢟ
ꢧ
ꢩ
ꢢ
ꢪ
ꢥ
ꢨ
ꢝ
ꢟ
ꢢ
ꢧ
ꢣ
ꢤ
ꢪ
ꢪ
ꢦ
ꢧ
ꢝ
ꢨ
ꢠ
ꢢ
ꢩ
ꢫ
ꢤ
ꢬ
ꢭ
ꢟ
ꢣ
ꢨ
ꢝ
ꢟ
ꢢ
ꢧ
ꢡ
ꢨ
ꢦ
ꢌ
ꢛ
ꢪ
ꢢ
ꢡ
ꢤ
ꢣ
ꢝ
ꢠ
ꢣ
ꢢ
ꢧ
ꢩ
ꢢ
ꢪ
ꢥ
ꢝ
ꢢ
ꢠ
ꢫ
ꢦ
ꢣ
ꢟ
ꢩ
ꢟ
ꢣ
ꢨ
ꢝ
ꢟ
ꢢ
ꢧ
ꢠ
ꢫ
ꢦ
ꢪ
ꢝ
ꢞ
ꢦ
ꢝ
ꢦ
ꢪ
ꢥ
ꢠ
ꢢ
ꢩ
ꢆ
ꢦ
ꢮ
ꢨ
ꢠ
ꢘ
ꢧ
ꢠ
ꢝ
ꢪ
ꢤ
ꢥ
ꢦ
ꢧ
ꢝ
ꢠ
ꢠ
ꢝ
ꢨ
ꢧ
ꢡ
ꢨ
ꢪ
ꢡ
ꢯ
ꢨ
ꢪ
ꢪ
ꢨ
ꢧ
ꢝ
ꢰ
ꢌ
ꢛ
ꢪ
ꢢ
ꢡ
ꢤ
ꢣ
ꢝ
ꢟ
ꢢ
ꢧ
ꢫꢨ ꢪ ꢨ ꢥ ꢦ ꢝ ꢦ ꢪ ꢠ ꢌ  
ꢫ
ꢪ
ꢢ
ꢣ
ꢦ
ꢠ
ꢠ
ꢟ
ꢧ
ꢱ
ꢡ
ꢢ
ꢦ
ꢠ
ꢧ
ꢢ
ꢝ
ꢧ
ꢦ
ꢣ
ꢦ
ꢠ
ꢠ
ꢨ
ꢪ
ꢟ
ꢭ
ꢰ
ꢟ
ꢧ
ꢣ
ꢭ
ꢤ
ꢡ
ꢦ
ꢝ
ꢦ
ꢠ
ꢝ
ꢟ
ꢧ
ꢱ
ꢢ
ꢩ
ꢨ
ꢭ
ꢭ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567

中文翻译

下载PDF

与SN74LVTT244J相关器件

型号 品牌 获取价格 描述 数据表
SN74LVTT244PWLE ROCHESTER

获取价格

 		LVT SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20, PLASTIC, TSSOP-20
SN74LVTT244PWR TI

获取价格

 		3.3-V ABT OCTAL BUFFERS/DRIVERS
SN74LVTT244W TI

获取价格

 		LVT SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, CDFP20, CERAMIC, DFP-20
SN74LVTZ240 TI

获取价格

 		3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN74LVTZ240DB TI

获取价格

 		LVT SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20, PLASTIC, SSOP-20
SN74LVTZ240DBLE TI

获取价格

 		3.3-V ABT Octal Buffers/Drivers With 3-State Outputs 20-SSOP -40 to 85
SN74LVTZ240DW TI

获取价格

 		3.3-V ABT Octal Buffers/Drivers With 3-State Outputs 20-SOIC -40 to 85
SN74LVTZ240DWR TI

获取价格

 		3.3-V ABT Octal Buffers/Drivers With 3-State Outputs 20-SOIC -40 to 85
SN74LVTZ240PW TI

获取价格

 		LVT SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20, PLASTIC, TSSOP-20
SN74LVTZ240PWLE TI

获取价格

 		3.3-V ABT Octal Buffers/Drivers With 3-State Outputs 20-TSSOP -40 to 85

与SN74LVTT244J相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证