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SN74LVTZ245 PDF预览

SN74LVTZ245

更新时间: 2024-09-10 11:58:15
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件信息通信管理
页数 文件大小 规格书
11页 227K
描述
3.3-V ABT OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

SN74LVTZ245 技术参数

生命周期:Obsolete包装说明:PLASTIC, SOP-20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84Is Samacsys:N
其他特性:WITH DIRECTION CONTROL系列:LVT
JESD-30 代码:R-PDSO-G20长度:12.8 mm
逻辑集成电路类型:BUS TRANSCEIVER位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE传播延迟(tpd):5.5 ns
座面最大高度:2.65 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:7.5 mmBase Number Matches:1

SN74LVTZ245 数据手册

 浏览型号SN74LVTZ245的Datasheet PDF文件第2页浏览型号SN74LVTZ245的Datasheet PDF文件第3页浏览型号SN74LVTZ245的Datasheet PDF文件第4页浏览型号SN74LVTZ245的Datasheet PDF文件第5页浏览型号SN74LVTZ245的Datasheet PDF文件第6页浏览型号SN74LVTZ245的Datasheet PDF文件第7页 
ꢋ ꢌꢋ ꢍꢅ ꢎꢏꢆ ꢐ ꢑꢆꢎꢄ ꢏꢒꢀ ꢆ ꢓꢎꢁꢀ ꢑꢔ ꢕ ꢅꢔ ꢓ  
SCBS303C − DECEMBER 1993 − REVISED JANUARY 1996  
SN54LVTZ245 . . . J PACKAGE  
SN74LVTZ245 . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
D State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low-Static Power  
Dissipation  
DIR  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
D High-Impedance State During Power Up  
OE  
B1  
B2  
B3  
B4  
B5  
and Power Down  
D Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V V  
)
CC  
D Support Unregulated Battery Operation  
Down to 2.7 V  
13 B6  
12 B7  
D Typical V  
(Output Ground Bounce)  
OLP  
< 0.8 V at V  
= 3.3 V, T = 25°C  
CC  
A
11  
GND  
B8  
D Latch-Up Performance Exceeds 500 mA  
Per JEDEC Standard JESD-17  
SN54LVTZ245 . . . FK PACKAGE  
(TOP VIEW)  
D Bus-Hold Data Inputs Eliminate the Need  
for External Pullup/Pulldown Resistors  
D Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK), and  
Ceramic (J) DIPs  
3
2
1
20 19  
18  
B1  
B2  
B3  
B4  
B5  
A3  
A4  
A5  
A6  
A7  
4
5
6
7
8
17  
16  
15  
14  
description  
9 10 11 12 13  
These octal bus transceivers are designed  
specifically for low-voltage (3.3-V) V operation,  
CC  
but with the capability to provide a TTL interface  
to a 5-V system environment.  
These devices are designed for asynchronous communication between data buses. They transmit data from  
the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the direction-control  
(DIR) input. The output-enable (OE) input can be used to disable the devices so the buses are effectively  
isolated.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74LVTZ245 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count  
and functionality of standard small-outline packages in less than half the printed-circuit-board area.  
The SN54LVTZ245 is characterized for operation over the full military temperature range of 55°C to 125°C.  
The SN74LVTZ245 is characterized for operation from 40°C to 85°C.  
FUNCTION TABLE  
INPUTS  
OPERATION  
OE  
L
DIR  
L
B data to A bus  
A data to B bus  
Isolation  
L
H
H
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢆꢥ  
Copyright 1996, Texas Instruments Incorporated  
ꢡ ꢥ ꢢ ꢡꢚ ꢛꢮ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢌ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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