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SN74LVTZ240PWLE PDF预览

SN74LVTZ240PWLE

更新时间: 2024-11-14 13:01:51
品牌 Logo 应用领域
德州仪器 - TI 驱动器输出元件
页数 文件大小 规格书
10页 228K
描述
3.3-V ABT Octal Buffers/Drivers With 3-State Outputs 20-TSSOP -40 to 85

SN74LVTZ240PWLE 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete包装说明:TSSOP, TSSOP20,.25
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.91控制类型:ENABLE LOW
系列:LVTJESD-30 代码:R-PDSO-G20
长度:6.5 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.064 A
位数:4功能数量:2
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TR
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
最大电源电流(ICC):12 mAProp。Delay @ Nom-Sup:4.3 ns
传播延迟(tpd):5 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:BICMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

SN74LVTZ240PWLE 数据手册

 浏览型号SN74LVTZ240PWLE的Datasheet PDF文件第2页浏览型号SN74LVTZ240PWLE的Datasheet PDF文件第3页浏览型号SN74LVTZ240PWLE的Datasheet PDF文件第4页浏览型号SN74LVTZ240PWLE的Datasheet PDF文件第5页浏览型号SN74LVTZ240PWLE的Datasheet PDF文件第6页浏览型号SN74LVTZ240PWLE的Datasheet PDF文件第7页 
ꢌ ꢍꢌ ꢎꢅ ꢏꢐꢆ ꢑ ꢒꢆꢏꢄ ꢐꢓꢔ ꢔ ꢕꢖꢀꢗ ꢘ ꢖꢙ ꢅ ꢕꢖ  
ꢚ ꢙꢆ ꢛ ꢌ ꢎꢀꢆꢏꢆ ꢕ ꢑ ꢓꢆ ꢜꢓ ꢆ  
SCBS301B − SEPTEMBER 1993 − REVISED JULY 1995  
SN54LVTZ240 . . . J PACKAGE  
SN74LVTZ240 . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
D State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low-Static Power  
Dissipation  
1OE  
1A1  
2Y4  
1A2  
2Y3  
1A3  
2Y2  
1A4  
2Y1  
GND  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
D High-Impedance State During Power Up  
2OE  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
and Power Down  
D Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V V  
)
CC  
D Support Unregulated Battery Operation  
Down to 2.7 V  
13 2A2  
12 1Y4  
D Typical V  
(Output Ground Bounce)  
OLP  
< 0.8 V at V  
= 3.3 V, T = 25°C  
CC  
A
11  
2A1  
D Latch-Up Performance Exceeds 500 mA  
Per JEDEC Standard JESD-17  
SN54LVTZ240 . . . FK PACKAGE  
(TOP VIEW)  
D Bus-Hold Data Inputs Eliminate the Need  
for External Pullup Resistors  
D Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK), and  
Ceramic (J) DIPs  
3
2
1
20 19  
18  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
1A2  
2Y3  
1A3  
2Y2  
1A4  
4
5
6
7
8
17  
16  
15  
14  
description  
9 10 11 12 13  
These octal buffers and line drivers are designed  
specifically for low-voltage (3.3-V) V operation,  
CC  
but with the capability to provide a TTL interface  
to a 5-V system environment.  
These devices are organized as two 4-bit line drivers with separate output-enable (OE) inputs. When OE is low,  
the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the  
high-impedance state.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74LVTZ240 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count  
and functionality of standard small-outline packages in less than half the printed-circuit-board area.  
The SN54LVTZ240 is characterized for operation over the full military temperature range of 55°C to 125°C.  
The SN74LVTZ240 is characterized for operation from 40°C to 85°C.  
FUNCTION TABLE  
(each buffer)  
INPUTS  
OUTPUT  
Y
OE  
A
H
L
L
L
L
H
Z
H
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1995, Texas Instruments Incorporated  
ꢓ ꢁ ꢄꢕꢀꢀ ꢑ ꢆꢛ ꢕꢖꢚ ꢙꢀ ꢕ ꢁ ꢑꢆꢕꢘ ꢝꢞ ꢟꢠ ꢡꢢꢣ ꢤꢥꢦ ꢧꢝ ꢣꢢ ꢧꢝꢨ ꢟꢧꢠ ꢜꢖ ꢑ ꢘ ꢓ ꢒꢆ ꢙꢑ ꢁ  
ꢫꢨ ꢪ ꢨ ꢥ ꢦ ꢝ ꢦ ꢪ ꢠ ꢍ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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