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SN74LVTZ240

更新时间： 2024-01-28 19:55:21
品牌 Logo 应用领域
德州仪器 - TI 驱动器输出元件
页数 文件大小 规格书
10页 228K
描述
3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

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SN74LVTZ240 数据手册

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SCBS301B − SEPTEMBER 1993 − REVISED JULY 1995  
SN54LVTZ240 . . . J PACKAGE  
SN74LVTZ240 . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
D State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low-Static Power  
Dissipation  
1OE  
1A1  
2Y4  
1A2  
2Y3  
1A3  
2Y2  
1A4  
2Y1  
GND  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
D High-Impedance State During Power Up  
2OE  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
and Power Down  
D Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V V  
)
CC  
D Support Unregulated Battery Operation  
Down to 2.7 V  
13 2A2  
12 1Y4  
D Typical V  
(Output Ground Bounce)  
OLP  
< 0.8 V at V  
= 3.3 V, T = 25°C  
CC  
A
11  
2A1  
D Latch-Up Performance Exceeds 500 mA  
Per JEDEC Standard JESD-17  
SN54LVTZ240 . . . FK PACKAGE  
(TOP VIEW)  
D Bus-Hold Data Inputs Eliminate the Need  
for External Pullup Resistors  
D Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK), and  
Ceramic (J) DIPs  
3
2
1
20 19  
18  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
1A2  
2Y3  
1A3  
2Y2  
1A4  
4
5
6
7
8
17  
16  
15  
14  
description  
9 10 11 12 13  
These octal buffers and line drivers are designed  
specifically for low-voltage (3.3-V) V operation,  
CC  
but with the capability to provide a TTL interface  
to a 5-V system environment.  
These devices are organized as two 4-bit line drivers with separate output-enable (OE) inputs. When OE is low,  
the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the  
high-impedance state.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74LVTZ240 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count  
and functionality of standard small-outline packages in less than half the printed-circuit-board area.  
The SN54LVTZ240 is characterized for operation over the full military temperature range of −55°C to 125°C.  
The SN74LVTZ240 is characterized for operation from −40°C to 85°C.  
FUNCTION TABLE  
(each buffer)  
INPUTS  
OUTPUT  
Y
OE  
A
H
L
L
L
L
H
Z
H
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1995, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...10

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与SN74LVTZ240相关器件

型号 品牌 获取价格 描述 数据表
SN74LVTZ240DB TI

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 		LVT SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20, PLASTIC, SSOP-20
SN74LVTZ240DBLE TI

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 		3.3-V ABT Octal Buffers/Drivers With 3-State Outputs 20-SSOP -40 to 85
SN74LVTZ240DW TI

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 		3.3-V ABT Octal Buffers/Drivers With 3-State Outputs 20-SOIC -40 to 85
SN74LVTZ240DWR TI

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 		3.3-V ABT Octal Buffers/Drivers With 3-State Outputs 20-SOIC -40 to 85
SN74LVTZ240PW TI

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 		LVT SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20, PLASTIC, TSSOP-20
SN74LVTZ240PWLE TI

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 		3.3-V ABT Octal Buffers/Drivers With 3-State Outputs 20-TSSOP -40 to 85
SN74LVTZ244 TI

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 		3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN74LVTZ244DBLE TI

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 		3.3-V ABT Octal Buffers/Drivers With 3-State Outputs 20-SSOP -40 to 85
SN74LVTZ244DBR TI

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 		具有总线保持、TTL 兼容型 CMOS 输入和三态输出的 8 通道、2.7V 至 3.6V
SN74LVTZ244DBRE4 TI

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 		LVT SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20, GREEN, PLASTIC, SSOP-20

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