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SN74LVTR245NSR PDF预览

SN74LVTR245NSR

更新时间： 2024-01-02 01:53:26
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德州仪器 - TI 总线收发器输出元件
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SN74LVTR245NSR 数据手册

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SN54LVTR245, SN74LVTR245  
3.3-V ABT OCTAL BUS TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCAS428 – OCTOBER 1993  
SN54LVTR245 . . . J PACKAGE  
SN74LVTR245 . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
• State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low-Static Power  
Dissipation  
DIR  
A1  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
• Supports Mixed-Mode Signal Operation  
OE  
B1  
B2  
B3  
B4  
B5  
(5-V Input and Output Voltages With  
A2  
A3  
A4  
A5  
3.3-V V  
)
CC  
• Supports Unregulated Battery Operation  
Down to 2.7 V  
• Typical V  
(Output Ground Bounce)  
A6  
OLP  
< 0.8 V at V  
= 3.3 V, T = 25°C  
A7  
A8  
13 B6  
12 B7  
CC  
A
• Latch-Up Performance Exceeds 500 mA  
11  
GND  
B8  
Per JEDEC Standard JESD-17  
• Bus-Hold Data Inputs Eliminate the Need  
for External Pullup Resistors  
SN54LVTR245 . . . FK PACKAGE  
(TOP VIEW)  
• Reduced Output Structure on A Port  
Minimizes V  
OHV  
• Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK), and  
Ceramic DIPs (J)  
3
2
1
20 19  
18  
B1  
B2  
B3  
B4  
B5  
A3  
A4  
A5  
A6  
A7  
4
5
6
7
8
17  
16  
15  
14  
description  
9 10 11 12 13  
These octal bus transceivers are designed  
specifically for low-voltage (3.3-V) V operation,  
CC  
but with the capability to provide a TTL interface to  
a 5-V system environment.  
The ′LVTR245 is designed for asynchronous communication between data buses. The device transmits data  
from the A bus to the B bus or from the B bus to the A bus depending upon the logic level at the direction-control  
(DIR) input. The output-enable (OE) input can be used to disable the device so the buses are effectivelyisolated.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The A port is designed to minimize the undershoot exhibited on high to low transition during simultaneous  
switching conditions.  
The SN74LVTR245 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count  
and functionality of standard small-outline packages in less than half the printed-circuit-board area.  
The SN54LVTR245 is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74LVTR245 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
INPUTS  
OPERATION  
OE  
L
DIR  
L
B data to A bus  
A data to B bus  
Isolation  
L
H
H
X
Copyright 1993, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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SN74LVTR245NSR 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVTR245DWR TI

功能相似

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SN74LVTR245DW TI

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SN74LVTT240DBLE TI

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SN74LVTT240DBR TI

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 		LVT SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20, SSOP-20
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SN74LVTT240DWR TI

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 		LVT SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20, PLASTIC, SO-20
SN74LVTT240J TI

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 		LVT SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, CDIP20, CERAMIC, DIP-20
SN74LVTT240OR TI

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 		3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

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