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SN74LVTT240J PDF预览

SN74LVTT240J

更新时间： 2024-11-14 20:48:19
品牌 Logo 应用领域
德州仪器 - TI 驱动信息通信管理输出元件逻辑集成电路
页数 文件大小 规格书
6页 111K
描述
LVT SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, CDIP20, CERAMIC, DIP-20

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SN74LVTT240J 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP,针数：20
Reach Compliance Code：unknown风险等级：5.56
系列：LVTJESD-30 代码：R-GDIP-T20
长度：24.195 mm逻辑集成电路类型：BUS DRIVER
位数：4功能数量：2
端口数量：2端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：INVERTED
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
传播延迟（tpd）：4 ns认证状态：Not Qualified
座面最大高度：5.08 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：NO技术：BICMOS
温度等级：INDUSTRIAL端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
宽度：7.62 mmBase Number Matches：1

SN74LVTT240J 数据手册

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SCES005 − FEBRUARY 1995  
SN54LVTT240 . . . J OR W PACKAGE  
SN74LVTT240 . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
• State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low-Static Power  
Dissipation  
1OE  
1A1  
2Y4  
1A2  
2Y3  
1A3  
2Y2  
1A4  
2Y1  
GND  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
• Supports Mixed-Mode Signal Operation  
2OE  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
(5-V Input and Output Voltages With  
3.3-V V  
)
CC  
• Supports Unregulated Battery Operation  
Down to 2.7 V  
• Typical V  
(Output Ground Bounce)  
OLP  
< 0.8 V at V  
= 3.3 V, T = 25°C  
13 2A2  
12 1Y4  
CC  
A
• Latch-Up Performance Exceeds 500 mA  
11  
2A1  
Per JEDEC Standard JESD-17  
• Supports Live Insertion  
SN54LVTT240 . . . FK PACKAGE  
(TOP VIEW)  
• Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK),  
Ceramic Flat (W) Packages, and Ceramic  
(J) DIPs  
3
2
1
20 19  
18  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
1A2  
2Y3  
1A3  
2Y2  
1A4  
4
5
6
7
8
17  
16  
15  
14  
description  
These octal buffers and line drivers are designed  
specifically for low-voltage (3.3-V) V operation,  
9 10 11 12 13  
CC  
but with the capability to provide a TTL interface to  
a 5-V system environment.  
The ’LVTT240 is organized as two 4-bit buffer/line  
drivers with separate output-enable (OE) inputs.  
When OE is low, the device passes data from the  
A inputs to the Y outputs. When OE is high, the  
outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
The SN74LVTT240 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count  
and functionality of standard small-outline packages in less than half the printed-circuit-board area.  
The SN54LVTT240 is characterized for operation over the full military temperature range of −55°C to 125°C.  
The SN74LVTT240 is characterized for operation from −40°C to 85°C.  
FUNCTION TABLE  
(each buffer)  
INPUTS  
OUTPUT  
Y
OE  
A
H
L
L
L
L
H
Z
H
X
Copyright 1995, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
123456

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