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SN74LVTT244DWR PDF预览

SN74LVTT244DWR

更新时间： 2024-11-14 19:43:03
品牌 Logo 应用领域
德州仪器 - TI 驱动信息通信管理光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
7页 145K
描述
LVT SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20, PLASTIC, SOP-20

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SN74LVTT244DWR 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP, SOP20,.4针数：20
Reach Compliance Code：unknown风险等级：5.63
控制类型：ENABLE LOW系列：LVT
JESD-30 代码：R-PDSO-G20长度：12.8 mm
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.064 A
位数：4功能数量：2
端口数量：2端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP20,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE包装方法：TAPE AND REEL
电源：3.3 VProp。Delay @ Nom-Sup：4.1 ns
传播延迟（tpd）：5.2 ns认证状态：Not Qualified
座面最大高度：2.65 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL宽度：7.5 mm
Base Number Matches：1

SN74LVTT244DWR 数据手册

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SCES006 − FEBRUARY 1995  
SN54LVTT244 . . . J OR W PACKAGE  
SN74LVTT244 . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
• State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low-Static Power  
Dissipation  
1OE  
1A1  
2Y4  
1A2  
2Y3  
1A3  
2Y2  
1A4  
2Y1  
GND  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
• Support Mixed-Mode Signal Operation (5-V  
2OE  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
Input and Output Voltages With 3.3-V V  
)
CC  
• Support Unregulated Battery Operation  
Down to 2.7 V  
• Typical V  
(Output Ground Bounce)  
OLP  
< 0.8 V at V  
= 3.3 V, T = 25°C  
CC  
A
13 2A2  
12 1Y4  
• Latch-Up Performance Exceeds 500 mA  
Per JEDEC Standard JESD-17  
11  
2A1  
• Supports Live Insertion  
• Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK),  
Ceramic Flat (W) Packages, and Ceramic  
(J) DIPs  
SN54LVTT244 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
1A2  
2Y3  
1A3  
2Y2  
1A4  
4
5
6
7
8
description  
17  
16  
15  
14  
These octal buffers and line drivers are designed  
specifically for low-voltage (3.3-V) V operation,  
CC  
but with the capability to provide a TTL interface to  
a 5-V system environment.  
9 10 11 12 13  
The ’LVTT244 are organized as two 4-bit line  
drivers with separate output-enable (OE) inputs.  
When OE is low, the device passes data from the  
A inputs to the Y outputs. When OE is high, the  
outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
The SN74LVTT244 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count  
and functionality of standard small-outline packages in less than half the printed-circuit-board area.  
The SN54LVTT244 is characterized for operation over the full military temperature range of −55°C to 125°C.  
The SN74LVTT244 is characterized for operation from −40°C to 85°C.  
FUNCTION TABLE  
(each buffer)  
INPUTS  
OUTPUT  
Y
OE  
A
H
L
L
L
H
L
H
X
Z
Copyright 1995, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567

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与SN74LVTT244DWR相关器件

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SN74LVTT244PWR TI

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 		3.3-V ABT OCTAL BUFFERS/DRIVERS
SN74LVTT244W TI

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 		LVT SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, CDFP20, CERAMIC, DFP-20
SN74LVTZ240 TI

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 		3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN74LVTZ240DB TI

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 		LVT SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20, PLASTIC, SSOP-20
SN74LVTZ240DBLE TI

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 		3.3-V ABT Octal Buffers/Drivers With 3-State Outputs 20-SSOP -40 to 85
SN74LVTZ240DW TI

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 		3.3-V ABT Octal Buffers/Drivers With 3-State Outputs 20-SOIC -40 to 85
SN74LVTZ240DWR TI

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 		3.3-V ABT Octal Buffers/Drivers With 3-State Outputs 20-SOIC -40 to 85
SN74LVTZ240PW TI

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 		LVT SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20, PLASTIC, TSSOP-20

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