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SN74LVT16646DGGR

更新时间： 2024-09-09 23:06:23
品牌 Logo 应用领域
德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
12页 223K
描述
3.3V ABT 16 BIT BUS TRANSCEIVERS AND REGISTERS WITH 3 STATE OUTPUTS

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中文翻译

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SN74LVT16646DGGR 数据手册

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SCBS149D − JULY 1994 − REVISED MARCH 2004  
SN54LVT16646 . . . WD PACKAGE  
SN74LVT16646 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
D
D
Members of the Texas Instruments  
WidebusFamily  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low-Static Power  
Dissipation  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
1DIR  
1CLKAB  
1SAB  
GND  
1OE  
2
1CLKBA  
1SBA  
GND  
1B1  
3
D
D
D
D
D
D
D
D
D
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V V  
4
)
5
1A1  
1A2  
CC  
6
1B2  
Support Unregulated Battery Operation  
Down to 2.7 V  
7
V
V
CC  
CC  
8
1A3  
1A4  
1A5  
GND  
1A6  
1A7  
1A8  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
1B3  
1B4  
1B5  
GND  
1B6  
1B7  
1B8  
2B1  
2B2  
2B3  
GND  
2B4  
2B5  
2B6  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
9
= 3.3 V, T = 25°C  
A
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Bus-Hold Data Inputs Eliminate the Need  
for External Pullup Resistors  
I
and Power-Up 3-State Support Hot  
off  
Insertion  
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
Flowthrough Architecture Optimizes  
PCB Layout  
Latch-Up Performance Exceeds 500 mA  
Per JEDEC Standard JESD-17  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
V
V
CC  
CC  
2A7  
2A8  
GND  
2B7  
2B8  
GND  
2SBA  
2CLKBA  
2OE  
description/ordering information  
2SAB  
2CLKAB  
2DIR  
The ’LVT16646 devices are 16-bit bus  
transceivers and registers designed for  
low-voltage (3.3-V) V  
operation, but with the  
CC  
capability to provide a TTL interface to a 5-V  
system environment.  
These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is clocked  
into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1  
illustrates the four fundamental bus-management functions that can be performed with the ′LVT16646 devices.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
Tube  
SN74LVT16646DL  
SSOP − DL  
LVT16646  
Tape and reel  
SN74LVT16646DLR  
SN74LVT16646DGGR  
SNJ54LVT16646WD  
−40°C to 85°C  
−55°C to 125°C  
TSSOP − DGG Tape and reel  
CFP − WD Tube  
LVT16646  
SNJ54LVT16646WD  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available  
at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
Copyright 2004, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

中文翻译

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SN74LVT16646DGGR 替代型号

型号 品牌 替代类型 描述 数据表
CLVTH16646IDGGREP TI

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 3.3-V ABT 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SN74LVTH16646DGGR TI

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 3.3-V ABT 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

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