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SN74LVT16835DL

更新时间： 2024-09-09 23:06:23
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德州仪器 - TI 驱动器输出元件
页数 文件大小 规格书
7页 111K
描述
3.3-V ABT 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

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SN74LVT16835DL 数据手册

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SN74LVT16835  
3.3-V ABT 18-BIT UNIVERSAL BUS DRIVER  
WITH 3-STATE OUTPUTS  
SCBS309D – MARCH 1994 – REVISED NOVEMBER 1996  
DGG OR DL PACKAGE  
(TOP VIEW)  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low-Static Power  
Dissipation  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
NC  
NC  
GND  
NC  
2
Member of the Texas Instruments  
Widebus Family  
3
Y1  
A1  
4
GND  
Y2  
GND  
A2  
Supports Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
5
6
Y3  
A3  
3.3-V V  
)
CC  
7
V
V
A4  
CC  
Y4  
CC  
Supports Unregulated Battery Operation  
Down to 2.7 V  
8
9
Y5  
Y6  
A5  
A6  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
OLP  
= 3.3 V, T = 25°C  
GND  
Y7  
Y8  
GND  
A7  
A8  
CC  
A
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
Y9  
A9  
Y10  
Y11  
Y12  
GND  
Y13  
Y14  
Y15  
A10  
A11  
A12  
GND  
A13  
A14  
A15  
Supports Live Insertion  
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
Flow-Through Architecture Optimizes  
PCB Layout  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages Using 25-mil  
Center-to-Center Spacings  
V
V
CC  
CC  
Y16  
Y17  
GND  
Y18  
OE  
A16  
A17  
GND  
A18  
CLK  
GND  
description  
The SN74LVT16835 is an 18-bit universal bus  
driver designed for low-voltage (3.3-V) V  
LE  
CC  
operation, but with the capability to provide a TTL  
interface to a 5-V system environment.  
NC – No internal connection  
Data flow from A to Y is controlled by the  
output-enable (OE) input. This device operates in  
the transparent mode when the latch-enable (LE)  
input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the  
A-bus data is stored in the latch/flip-flop on the low-to-high transition of the clock. When OE is high, the outputs  
are in the high-impedance state.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
The SN74LVT16835 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG) packages,  
which provide twice the input/output (I/O) pins and functionality of standard small-outline packages in the same  
printed circuit board area.  
The SN74LVT16835 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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