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SCBS134K − SEPTEMBER 1992 − REVISED JANUARY 2004
DB, DGV, DW, NS, OR PW PACKAGE
(TOP VIEW)
D
Supports Mixed-Mode Signal Operation
(5-V Input and Output Voltages With 3.3-V
V
)
CC
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
D
D
D
D
D
Supports Unregulated Battery Operation
Down To 2.7 V
2OE
1Y1
2A4
1Y2
2A3
1Y3
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
= 3.3 V, T = 25°C
A
I
and Power-Up 3-State Support Hot
off
Insertion
13 2A2
12 1Y4
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
11
2A1
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
This octal buffer and line driver is designed specifically for low-voltage (3.3-V) V
capability to provide a TTL interface to a 5-V system environment.
operation, but with the
CC
The SN74LVT240A is organized as two 4-bit buffer/line drivers with separate output-enable (OE) inputs. When
OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the
high-impedance state.
When V
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup resistor;
CC
This device is fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube
SN74LVT240ADW
SN74LVT240ADWR
SN74LVT240ANSR
SN74LVT240ADBR
SN74LVT240APW
SN74LVT240APWR
SN74LVT240ADGVR
SOIC − DW
LVT240A
Tape and reel
Tape and reel
Tape and reel
Tube
SOP − NS
LVT240A
LX240A
SSOP − DB
−40°C to 85°C
TSSOP − PW
TVSOP − DGV
LX240A
LX240A
Tape and reel
Tape and reel
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
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