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SN74LVT240APWRG4 PDF预览

SN74LVT240APWRG4

更新时间： 2024-11-20 05:16:59
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
15页 454K
描述
3.3-V ABT OCTAL SUFFER/DRIBVER WITH 3-STATE OUTPUTS

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SN74LVT240APWRG4 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：GREEN, PLASTIC, TSSOP-20针数：20
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.38Is Samacsys：N
控制类型：ENABLE LOW系列：LVT
JESD-30 代码：R-PDSO-G20JESD-609代码：e4
长度：6.5 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.064 A
湿度敏感等级：1位数：4
功能数量：2端口数量：2
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：INVERTED封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP20,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TR峰值回流温度（摄氏度）：260
电源：3.3 VProp。Delay @ Nom-Sup：4 ns
传播延迟（tpd）：4.6 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4.4 mm
Base Number Matches：1

SN74LVT240APWRG4 数据手册

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SCBS134K − SEPTEMBER 1992 − REVISED JANUARY 2004  
DB, DGV, DW, NS, OR PW PACKAGE  
(TOP VIEW)  
D
Supports Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With 3.3-V  
V
)
CC  
1OE  
1A1  
2Y4  
1A2  
2Y3  
1A3  
2Y2  
1A4  
2Y1  
GND  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
D
D
D
D
D
Supports Unregulated Battery Operation  
Down To 2.7 V  
2OE  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
A
I
and Power-Up 3-State Support Hot  
off  
Insertion  
13 2A2  
12 1Y4  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
11  
2A1  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
description/ordering information  
This octal buffer and line driver is designed specifically for low-voltage (3.3-V) V  
capability to provide a TTL interface to a 5-V system environment.  
operation, but with the  
CC  
The SN74LVT240A is organized as two 4-bit buffer/line drivers with separate output-enable (OE) inputs. When  
OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the  
high-impedance state.  
When V  
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.  
CC  
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup resistor;  
CC  
This device is fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry  
off  
off  
disables the outputs, preventing damaging current backflow through the device when it is powered down. The  
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,  
which prevents driver conflict.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
Tube  
SN74LVT240ADW  
SN74LVT240ADWR  
SN74LVT240ANSR  
SN74LVT240ADBR  
SN74LVT240APW  
SN74LVT240APWR  
SN74LVT240ADGVR  
SOIC − DW  
LVT240A  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP − NS  
LVT240A  
LX240A  
SSOP − DB  
−40°C to 85°C  
TSSOP − PW  
TVSOP − DGV  
LX240A  
LX240A  
Tape and reel  
Tape and reel  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2004, Texas Instruments Incorporated  
ꢙꢞ ꢝ ꢩꢤꢣ ꢡ ꢢ ꢣ ꢝꢛ ꢜꢝ ꢞ ꢟ ꢡ ꢝ ꢢ ꢦꢥ ꢣ ꢚꢜ ꢚꢣꢠ ꢡꢚ ꢝꢛꢢ ꢦꢥ ꢞ ꢡꢪ ꢥ ꢡꢥ ꢞ ꢟꢢ ꢝꢜ ꢆꢥꢫ ꢠꢢ ꢖꢛꢢ ꢡꢞ ꢤꢟ ꢥꢛꢡ ꢢ  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...15

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