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SN74LVT18504PMLE PDF预览

SN74LVT18504PMLE

更新时间: 2024-09-14 13:13:51
品牌 Logo 应用领域
德州仪器 - TI 总线收发器测试
页数 文件大小 规格书
32页 456K
描述
LVT SERIES, 20-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, PQFP64

SN74LVT18504PMLE 技术参数

生命周期:Obsolete包装说明:LFQFP,
Reach Compliance Code:unknown风险等级:5.56
其他特性:WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; WITH CLOCK ENABLE系列:LVT
JESD-30 代码:S-PQFP-G64长度:10 mm
负载电容(CL):50 pF逻辑集成电路类型:BOUNDARY SCAN REG BUS TRANSCEIVER
位数:20功能数量:1
端口数量:2端子数量:64
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
最大电源电流(ICC):30 mA传播延迟(tpd):8.5 ns
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:BICMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD宽度:10 mm
Base Number Matches:1

SN74LVT18504PMLE 数据手册

 浏览型号SN74LVT18504PMLE的Datasheet PDF文件第2页浏览型号SN74LVT18504PMLE的Datasheet PDF文件第3页浏览型号SN74LVT18504PMLE的Datasheet PDF文件第4页浏览型号SN74LVT18504PMLE的Datasheet PDF文件第5页浏览型号SN74LVT18504PMLE的Datasheet PDF文件第6页浏览型号SN74LVT18504PMLE的Datasheet PDF文件第7页 
ꢋ ꢌꢋ ꢍꢅ ꢎꢏꢆ ꢀꢐꢎ ꢁ ꢆ ꢑꢀꢆ ꢒ ꢑꢅ ꢓ ꢐ  
SCBS163F − AUGUST 1993 − REVISED JULY 1996  
D
D
D
Member of the Texas Instruments SCOPE   
D
Compatible With the IEEE Standard  
1149.1-1990 (JTAG) Test Access Port  
and Boundary-Scan Architecture  
Family of Testability Products  
Member of the Texas Instruments  
WidebusFamily  
State-of-the-Art 3.3-V ABT Design Supports  
Mixed-Mode Signal Operation (5-V Input  
D
SCOPE Instruction Set  
− IEEE Standard 1149.1-1990 Required  
Instructions and Optional CLAMP and  
HIGHZ  
and Output Voltages With 3.3-V V  
)
CC  
− Parallel-Signature Analysis at Inputs  
− Pseudo-Random Pattern Generation  
From Outputs  
− Sample Inputs/Toggle Outputs  
− Binary Count From Outputs  
− Device Identification  
D
D
Supports Unregulated Battery Operation  
Down to 2.7 V  
UBT (Universal Bus Transceiver)  
Combines D-Type Latches and D-Type  
Flip-Flops for Operation in Transparent,  
Latched, or Clocked Mode  
− Even-Parity Opcodes  
D
Bus-Hold Data Inputs Eliminate the Need  
for External Pullup Resistors  
D
Packaged in 64-Pin Plastic Thin Quad Flat  
Packages Using 0.5-mm Center-to-Center  
Spacings  
PM PACKAGE  
(TOP VIEW)  
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49  
A4  
A5  
A6  
GND  
A7  
A8  
B5  
B6  
B7  
GND  
B8  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
2
3
4
5
6
B9  
B10  
A9  
A10  
7
8
V
CC  
9
V
B11  
B12  
B13  
B14  
GND  
B15  
B16  
B17  
CC  
10  
11  
12  
13  
14  
15  
16  
A11  
A12  
A13  
GND  
A14  
A15  
A16  
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
SCOPE, Widebus, and UBT are trademarks of Texas Instruments Incorporated.  
ꢆꢦ  
Copyright 1996, Texas Instruments Incorporated  
ꢢ ꢦ ꢣ ꢢꢛ ꢜꢯ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢ ꢦ ꢟ ꢣ ꢌ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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