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SCBS162F − AUGUST 1993 − REVISED JULY 1996
D
D
D
Members of the Texas Instruments
SCOPE Family of Testability Products
Members of the Texas Instruments
Widebus Family
State-of-the-Art 3.3-V ABT Design Supports
Mixed-Mode Signal Operation (5-V Input
D
Compatible With the IEEE Standard
1149.1-1990 (JTAG) Test Access Port
and Boundary-Scan Architecture
D
SCOPE Instruction Set
− IEEE Standard 1149.1-1990 Required
Instructions and Optional CLAMP and
HIGHZ
and Output Voltages With 3.3-V V
)
CC
− Parallel-Signature Analysis at Inputs
− Pseudo-Random Pattern Generation
From Outputs
− Sample Inputs/Toggle Outputs
− Binary Count From Outputs
− Device Identification
D
D
Support Unregulated Battery Operation
Down to 2.7 V
UBT (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
− Even-Parity Opcodes
D
D
Bus-Hold Data Inputs Eliminate the Need
for External Pullup Resistors
D
Packaged in 64-Pin Plastic Thin Quad Flat
Packages Using 0.5-mm Center-to-Center
Spacings
B-Port Outputs of SN74LVT182502 Devices
Have Equivalent 25-Ω Series Resistors, So
No External Resistors Are Required
SN74LVT18502, SN74LVT182502 . . . PM PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1A3
1A4
1A5
GND
1A6
1A7
1A8
1A9
1B4
1B5
1B6
GND
1B7
1B8
1B9
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
2
3
4
5
6
7
8
V
CC
9
V
2B1
2B2
2B3
2B4
GND
2B5
2B6
2B7
CC
10
11
12
13
14
15
16
2A1
2A2
2A3
GND
2A4
2A5
2A6
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCOPE, Widebus, and UBT are trademarks of Texas Instruments Incorporated.
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Copyright 1996, Texas Instruments Incorporated
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ꢣ ꢧ ꢤ ꢣꢜ ꢝꢰ ꢟꢞ ꢢ ꢪꢪ ꢨꢢ ꢠ ꢢ ꢡ ꢧ ꢣ ꢧ ꢠ ꢤ ꢎ
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1
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