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SN74LV74A-Q1 PDF预览

SN74LV74A-Q1

更新时间： 2024-11-04 05:04:43
品牌 Logo 应用领域
德州仪器 - TI 触发器
页数 文件大小 规格书
10页 225K
描述
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

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中文翻译

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SN74LV74A-Q1 数据手册

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ꢀꢁ ꢂꢃ ꢄꢅ ꢂꢃ ꢆꢇ ꢈ ꢉ  
ꢊꢋꢆ ꢄ ꢌꢍ ꢀꢎ ꢏ ꢎꢅꢐ ꢇꢐꢊꢑ ꢐꢇꢏ ꢒꢎ ꢑ ꢑꢐ ꢒꢐꢊ ꢊꢇꢏ ꢓꢌ ꢐ ꢔꢄ ꢎꢌ ꢇ ꢔꢄꢍ ꢌ  
SCLS556A − DECEMBER 2003 − REVISED MAY 2004  
D OR PW PACKAGE  
(TOP VIEW)  
D
Qualification in Accordance With  
AEC-Q100  
†
D
Qualified for Automotive Applications  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1CLR  
1D  
V
CC  
2CLR  
2D  
D
Customer-Specific Configuration Control  
Can Be Supported Along With  
Major-Change Approval  
1CLK  
1PRE  
1Q  
2CLK  
2PRE  
2Q  
D
D
D
2-V to 5.5-V V  
Operation  
CC  
1Q  
Max t of 13 ns at 5 V  
pd  
8
GND  
2Q  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
A
D
D
D
D
D
Typical V  
>2.3 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
A
Support Mixed-Mode Voltage Operation on  
All Ports  
I
Supports Partial-Power-Down Mode  
off  
Operation  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
†
Contact factory for details. Q100 qualification data available on  
request.  
description/ordering informationS  
This dual positive-edge-triggered D-type flip-flop is designed for 2-V to 5.5-V V  
operation.  
CC  
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the  
other inputs. When PRE and CLR are inactive (high), data at the data (D) inputs meeting the setup-time  
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs  
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,  
data at the D input can be changed without affecting the levels at the outputs.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
‡
PACKAGE  
T
A
SOIC − D  
Tape and reel SN74LV74AQDRQ1  
Tape and reel SN74LV74AQPWRQ1  
LV74A  
LV74A  
−40°C to 125°C  
TSSOP − PW  
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2004, Texas Instruments Incorporated  
ꢌꢚ ꢙ ꢥꢠꢟ ꢝ ꢞ ꢟ ꢙꢗ ꢘꢙ ꢚ ꢛ ꢝ ꢙ ꢞ ꢢꢡ ꢟ ꢖꢘ ꢖꢟꢜ ꢝꢖ ꢙꢗꢞ ꢢꢡ ꢚ ꢝꢧ ꢡ ꢝꢡ ꢚ ꢛꢞ ꢙꢘ ꢏꢡꢨ ꢜꢞ ꢎꢗꢞ ꢝꢚ ꢠꢛ ꢡꢗꢝ ꢞ  
ꢞ ꢝ ꢜ ꢗꢥ ꢜ ꢚꢥ ꢩ ꢜ ꢚꢚ ꢜ ꢗ ꢝꢪꢦ ꢌꢚ ꢙ ꢥꢠꢟ ꢝꢖꢙꢗ ꢢꢚ ꢙꢟ ꢡꢞ ꢞꢖ ꢗꢫ ꢥꢙꢡ ꢞ ꢗꢙꢝ ꢗꢡ ꢟꢡ ꢞꢞ ꢜꢚ ꢖꢤ ꢪ ꢖꢗꢟ ꢤꢠꢥ ꢡ  
ꢝ ꢡ ꢞ ꢝꢖ ꢗꢫ ꢙꢘ ꢜ ꢤꢤ ꢢꢜ ꢚ ꢜ ꢛ ꢡ ꢝ ꢡ ꢚ ꢞ ꢦ  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

中文翻译

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SN74LV74A-Q1 替代型号

型号 品牌 替代类型 描述 数据表
SN74LV74A-EP TI

功能相似

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