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SN74LV74DBR PDF预览

SN74LV74DBR

更新时间： 2024-11-02 15:52:19
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
8页 143K
描述
LV/LV-A/LVX/H SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, PLASTIC, SSOP-14

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SN74LV74DBR 技术参数

生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP,针数：14
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.7系列：LV/LV-A/LVX/H
JESD-30 代码：R-PDSO-G14长度：6.2 mm
逻辑集成电路类型：D FLIP-FLOP位数：1
功能数量：2端子数量：14
最高工作温度：85 °C最低工作温度：-40 °C
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH传播延迟（tpd）：28 ns
认证状态：Not Qualified座面最大高度：2 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL触发器类型：POSITIVE EDGE
宽度：5.3 mm最小 fmax：70 MHz
Base Number Matches：1

SN74LV74DBR 数据手册

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SCLS189C − FEBRUARY 1993 − REVISED APRIL 1996  
SN54LV74 . . . J OR W PACKAGE  
SN74LV74 . . . D, DP, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
EPIC (Enhanced-Performance Implanted  
CMOS) 2-µ Process  
Typical V  
(Output Ground Bounce)  
OLP  
< 0.8 V at V , T = 25°C  
CC  
A
1CLR  
1D  
V
CC  
2CLR  
2D  
1
2
3
4
5
6
7
14  
13  
12  
11  
Typical V  
(Output V  
Undershoot)  
OHV  
OH  
> 2 V at V , T = 25°C  
CC  
A
1CLK  
1PRE  
1Q  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model  
(C = 200 pF, R = 0)  
2CLK  
10 2PRE  
9
8
1Q  
2Q  
2Q  
GND  
D
D
Latch-Up Performance Exceeds 250 mA  
Per JEDEC Standard JESD-17  
SN54LV74 . . . FK PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW),  
Ceramic Flat (W) Packages, Chip Carriers  
(FK), and (J) 300-mil DIPs  
3
2
1
20 19  
18  
2D  
1CLK  
NC  
4
5
6
7
8
NC  
17  
16  
description  
2CLK  
1PRE  
NC  
15 NC  
14  
9 10 11 12 13  
These dual positive-edge-triggered D-type flip-  
flops are designed for 2.7-V to 5.5-V V  
operation.  
2PRE  
1Q  
CC  
A low level at the preset (PRE) or clear (CLR)  
inputs sets or resets the outputs regardless of the  
levels of the other inputs. When PRE and CLR are  
inactive (high), data at the data (D) inputs meeting  
the setup-time requirements is transferred to the  
NC − No internal connection  
outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly  
related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed  
without affecting the levels at the outputs.  
The SN74LV74 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count  
and functionality of standard small-outline packages in less than half the printed-circuit-board area.  
The SN54LV74 is characterized for operation over the full military temperature range of −55°C to 125°C. The  
SN74LV74 is characterized for operation from −40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
12345678

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