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SN74LV8151_08

更新时间： 2024-11-02 05:04:43
品牌 Logo 应用领域
德州仪器 - TI 触发器输出元件
页数 文件大小 规格书
15页 293K
描述
10-BIT UNIVERSAL SCHMITT-TRIGGER BUFFER WITH 3-STATE OUTPUTS

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中文翻译

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SN74LV8151_08 数据手册

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SCES610 − OCTOBER 2004  
NT OR PW PACKAGE  
(TOP VIEW)  
D
D
D
2-V to 5.5-V V  
Operation  
CC  
Max t of 15 ns at 5 V  
pd  
Schmitt-Trigger Inputs Allow for Slow Input  
Rise/Fall Time  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
1
T/C  
A
B
V
P
N
CC  
2
3
D
D
D
D
D
D
D
Polarity Control for Y Outputs Selects True  
or Complementary Logic  
4
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
Y7  
Y8  
OE  
5
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
6
= 3.3 V, T = 25°C  
A
7
Typical V  
>2.3 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
8
= 3.3 V, T = 25°C  
A
9
I
Supports Partial-Power-Down Mode  
off  
10  
11  
12  
Operation  
Supports Mixed-Mode Voltage Operation on  
All Ports  
GND  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
description/ordering information  
The SN74LV8151 is a 10-bit universal Schmitt-trigger buffer with 3-state outputs, designed for 2-V to 5.5-V V  
CC  
operation. The logic control (T/C) pin allows the user to configure Y1 to Y8 as noninverting or inverting outputs.  
When T/C is high, the Y outputs are noninverted (true logic ), and when T/C is low, the Y outputs are inverted  
(complementary logic).  
When output-enable (OE) input is low, the device passes data from Dn to Yn. When OE is high, the Y outputs  
are in the high-impedance state. The path A to P is a simple Schmitt-trigger buffer, and the path B to N is a simple  
Schmitt-trigger inverter.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
To ensure the high-impedance state during power up or power down, OE should be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP − NT  
Tube  
Tube  
SN74LV8151NT  
SN74LV8151PW  
SN74LV8151NT  
−40°C to 85°C  
TSSOP − PW  
LV8151  
Tape and reel SN74LV8151PWR  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2004, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...15

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