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SN74LV8153PWRE4 PDF预览

SN74LV8153PWRE4

更新时间： 2024-11-23 23:03:19
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
13页 209K
描述
SERIAL-TO-PARALLEL INTERFACE

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中文翻译

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SN74LV8153PWRE4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP20针数：20
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.68计数方向：RIGHT
系列：LV/LV-A/LVX/HJESD-30 代码：R-PDSO-G20
JESD-609代码：e4长度：6.5 mm
逻辑集成电路类型：SERIAL IN PARALLEL OUT湿度敏感等级：1
位数：8功能数量：1
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：4.4 mm
Base Number Matches：1

SN74LV8153PWRE4 数据手册

 浏览型号SN74LV8153PWRE4的Datasheet PDF文件第2页浏览型号SN74LV8153PWRE4的Datasheet PDF文件第3页浏览型号SN74LV8153PWRE4的Datasheet PDF文件第4页浏览型号SN74LV8153PWRE4的Datasheet PDF文件第5页浏览型号SN74LV8153PWRE4的Datasheet PDF文件第6页浏览型号SN74LV8153PWRE4的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ  
ꢀꢊ ꢋꢌꢍ ꢄꢎꢏꢐ ꢎꢑꢍꢋꢍ ꢄꢄ ꢊꢄ ꢌꢁꢏ ꢊꢋ ꢒꢍ ꢓꢊ  
www.ti.com  
SCLS555 − JUNE 2004  
DESCRIPTION  
FEATURES  
D
D
D
Single-Wire Serial Data Input  
The SN74LV8153 is a serial-to-parallel data converter. It  
accepts serial input data and outputs 8-bit parallel data.  
Compatible With UART Serial-Data Format  
Up to Eight Devices (64-Bit Parallel) Can  
Share the Same Bus by Using Different  
Combinations of A0, A1, A2  
The automatic data-rate detection feature of the  
SN74LV8153 eliminates the need for an external oscillator  
and helps with cost and board real-estate savings.  
D
D
D
D
D
D
Up to 40 mA Current Drive in Open-Collector  
Mode for Driving LEDs  
The OUTSEL pin is used to choose between open  
collector and push-pull outputs. The open-collector option  
is suitable when this device is used in applications such as  
LED interface, where high drive current is required. SOUT  
is the output that acknowledges reception of the serial  
data.  
Outputs Can be Configured as  
Open-Collector or Push-Pull  
Internal Oscillator and Counter for  
Automatic Data-Rate Detection  
Output Levels Are Referenced to V  
and  
CC2  
To ensure the high-impedance state during power up or  
Can Be Configured From 3 V to 12 V  
power down, OE should be tied to V  
through a pullup  
CC1  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
resistor; the minimum value of the resistor is determined  
by the current-sinking capability of the driver.  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 1000-V Charged-Device Model (C101)  
N OR PW PACKAGE  
(TOP VIEW)  
V
1
2
3
4
5
6
7
8
9
10  
20  
19 Y0  
18  
V
SUMMARY OF RECOMMENDED  
OPERATING CONDITIONS  
CC1  
A0  
CC2  
A1  
A2  
D
Y1  
PARAMETER  
17 Y2  
16 Y3  
15 Y4  
14 Y5  
V
V
3 V to 5.5 V  
CC1  
OUTSEL  
RESET  
OE  
3 V to 13.2 V  
CC2  
40 mA @ V  
CC2  
= 4.5 V  
I
OL  
OH  
(open-collector mode)  
13  
12  
11  
Y6  
Y7  
GND  
−24 mA @ V = 12 V  
SOUT  
GND  
CC2  
I
(push-pull mode)  
Maximum Data Rate  
24 Kbps  
FUNCTION TABLE  
(each buffer)  
INPUTS  
OUTSEL RESET  
OUTPUT  
OUTPUT  
STRUCTURE  
Yn  
OE  
L
Dn  
H
L
L
L
H
H
X
L
L
H
H
H
H
L
L
Open collector  
Push-pull  
L
H
X
L
X
X
H
L
L
H
H
H
H
H
H
X
L
L
H
L
X
X
Z
L
In the open-collector mode (OUTSEL = L), the outputs are inverted,  
e.g., Y1 = l, when D1 = H  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments  
semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢑꢋ ꢐ ꢔꢕ ꢓ ꢏꢌ ꢐꢁ ꢔ ꢍꢏꢍ ꢖꢗ ꢘꢙ ꢚ ꢛꢜ ꢝꢖꢙꢗ ꢖꢞ ꢟꢠ ꢚ ꢚ ꢡꢗꢝ ꢜꢞ ꢙꢘ ꢢꢠꢣ ꢤꢖꢟ ꢜꢝꢖ ꢙꢗ ꢥꢜ ꢝꢡꢦ ꢑꢚ ꢙꢥꢠ ꢟꢝꢞ  
ꢟ ꢙꢗ ꢘꢙꢚ ꢛ ꢝꢙ ꢞ ꢢꢡ ꢟ ꢖ ꢘꢖ ꢟ ꢜ ꢝꢖ ꢙꢗꢞ ꢢ ꢡꢚ ꢝꢧꢡ ꢝꢡ ꢚ ꢛꢞ ꢙꢘ ꢏꢡꢨ ꢜꢞ ꢌꢗꢞ ꢝꢚ ꢠꢛ ꢡꢗꢝ ꢞ ꢞꢝ ꢜꢗꢥ ꢜꢚ ꢥ ꢩ ꢜꢚ ꢚ ꢜ ꢗꢝꢪꢦ  
ꢑꢚ ꢙ ꢥꢠꢟ ꢝ ꢖꢙ ꢗ ꢢꢚ ꢙ ꢟ ꢡ ꢞ ꢞ ꢖꢗ ꢫ ꢥꢙ ꢡ ꢞ ꢗꢙꢝ ꢗꢡ ꢟꢡ ꢞꢞ ꢜꢚ ꢖꢤ ꢪ ꢖꢗꢟ ꢤꢠꢥ ꢡ ꢝꢡ ꢞꢝꢖ ꢗꢫ ꢙꢘ ꢜꢤ ꢤ ꢢꢜ ꢚ ꢜꢛ ꢡꢝꢡ ꢚ ꢞꢦ  
Copyright 2004, Texas Instruments Incorporated  
1234567...13

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