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SN74LV8154-EP

更新时间： 2024-02-06 01:07:14
品牌 Logo 应用领域
德州仪器 - TI 计数器输出元件
页数 文件大小 规格书
15页 562K
描述
DUAL 16 BIT BINARY COUNTER WITH 3-STATE OUTPUT REGISTERS

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SN74LV8154-EP 数据手册

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SCLS704A − JULY 2006 − REVISED SEPTEMBER 2007  
D
Controlled Baseline  
− One Assembly Site  
− One Test Site  
D
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
− One Fabrication Site  
− 1000-V Charged-Device Model (C101)  
†
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, Highly  
Accelerated Stress Test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life. Such qualification  
testing should not be viewed as justifying use of this component  
beyond specified performance and environmental limits.  
D
D
Extended Temperature Performance of  
−55°C to 125°C  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
D
D
D
Enhanced Product-Change Notification  
†
Qualification Pedigree  
Can Be Used as Two 16 Bit Counters or a  
Single 32 Bit Counter  
PW PACKAGE  
(TOP VIEW)  
D
D
D
2-V to 5.5-V V  
Operation  
CC  
CLKA  
CLKB  
GAL  
GAU  
GBL  
1
2
3
4
5
6
7
8
9
10  
20  
V
CC  
Max t of 25 ns at 5 V (RCLK to Y)  
pd  
19 Y0  
18 Y1  
17 Y2  
Typical V  
<0.7 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 5 V, T = 25°C  
A
D
D
D
Typical V  
>4.4 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
16  
Y3  
= 5 V, T = 25°C  
A
GBU  
15 Y4  
I
Supports Partial-Power-Down Mode  
14  
13  
12  
11  
RCLK  
RCOA  
CLKBEN  
GND  
Y5  
Y6  
Y7  
CCLR  
off  
Operation  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
description/ordering information  
The SN74LV8154 is a dual 16 bit binary counter with 3-state output registers, designed for 2-V to 5.5-V V  
operation.  
CC  
This 16 bit counter (A or B) feeds a 16 bit storage register and each storage register is further divided into an  
upper byte and lower byte. The GAL, GAU, GBL, and GBU inputs are used to select the byte that needs to be  
output at Y0−Y7. CLKA is the clock for A counter and CLKB is the clock for B counter. RCLK is the clock for the  
A and B storage registers. All three clock signals are positive-edge triggered.  
A 32 bit counter can be realized by connecting CLKA and CLKB together and by connecting RCOA to CLKBEN.  
To ensure the high-impedance state during power up or power down, GAL, GAU, GBL, and GBU should be tied  
to V through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability  
CC  
of the driver.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
†
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
}
T
A
PACKAGE  
−55°C to 125°C  
TSSOP − PW Tape and reel  
SN74LV8154MPWREP  
LV8154ME  
†
‡
For the most current package and ordering information, see the Package Option Addendum at the  
end of this document, or see the TI website at www.ti.com.  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/packaging.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2007, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...15

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