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SN74LV86A-EP PDF预览

SN74LV86A-EP

更新时间: 2024-01-29 09:04:57
品牌 Logo 应用领域
德州仪器 - TI 输入元件
页数 文件大小 规格书
11页 512K
描述
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE

SN74LV86A-EP 数据手册

 浏览型号SN74LV86A-EP的Datasheet PDF文件第2页浏览型号SN74LV86A-EP的Datasheet PDF文件第3页浏览型号SN74LV86A-EP的Datasheet PDF文件第4页浏览型号SN74LV86A-EP的Datasheet PDF文件第5页浏览型号SN74LV86A-EP的Datasheet PDF文件第6页浏览型号SN74LV86A-EP的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢊꢋ  
ꢌ ꢍꢈꢎꢏ ꢍꢋꢄ ꢊ ꢐ ꢉꢑꢁ ꢋꢍꢒ ꢊꢓ ꢔꢄ ꢍꢀꢑ ꢅꢊ ꢉꢕ ꢏ ꢖ ꢈꢒꢊ  
SCLS567A − JANUARY 2004 − REVISED MAY 2004  
D
Controlled Baseline  
− One Assembly/Test Site, One Fabrication  
Site  
D
D
D
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
CC A  
Typical V  
>2.3 V at V  
(Output V  
Undershoot)  
OHV  
OH  
D
D
Extended Temperature Performance of  
−40°C to 105°C  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
= 3.3 V, T = 25°C  
CC A  
Supports Mixed-Mode Voltage Operation on  
All Ports  
PW PACKAGE  
(TOP VIEW)  
D
D
D
Enhanced Product-Change Notification  
Qualification Pedigree  
1A  
1B  
1
2
3
4
5
6
7
V
CC  
4B  
2-V to 5.5-V V  
Operation  
14  
13  
CC  
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, Highly  
Accelerated Stress Test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life. Such qualification  
testing should not be viewed as justifying use of this component  
beyond specified performance and environmental limits.  
1Y  
12 4A  
11  
10  
9
2A  
4Y  
3B  
3A  
3Y  
2B  
2Y  
8
GND  
description/ordering information  
The SN74LV86A is a quadruple 2-input exclusive-OR gate designed for 2-V to 5.5-V V  
operation.  
CC  
This device contains four independent 2-input exclusive-OR gates. It performs the Boolean function  
Y = A ę B or Y = AB + AB in positive logic.  
A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced  
in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the  
output.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
T
PACKAGE  
TSSOP − PW  
A
−40°C to 105°C  
Tape and reel SN74LV86ATPWREP  
LV86AEP  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
FUNCTION TABLE  
(each gate)  
INPUTS  
OUTPUT  
Y
A
B
L
L
L
L
H
H
L
H
L
H
H
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢒꢢ  
Copyright 2004, Texas Instruments Incorporated  
ꢞ ꢢ ꢟ ꢞꢗ ꢘꢬ ꢚꢙ ꢝ ꢥꢥ ꢣꢝ ꢛ ꢝ ꢜ ꢢ ꢞ ꢢ ꢛ ꢟ ꢧ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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