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SN74LV74DBLE PDF预览

SN74LV74DBLE

更新时间： 2024-10-01 13:13:51
品牌 Logo 应用领域
德州仪器 - TI 触发器
页数 文件大小 规格书
7页 139K
描述
Dual Positive-Edge-Triggered D-Type Flip-Flop 14-SSOP -40 to 85

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中文翻译

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SN74LV74DBLE 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP, SSOP14,.3针数：14
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.77系列：LV/LV-A/LVX/H
JESD-30 代码：R-PDSO-G14长度：6.2 mm
负载电容（CL）：50 pF逻辑集成电路类型：D FLIP-FLOP
最大频率@ Nom-Sup：24000000 Hz最大I（ol）：0.006 A
位数：1功能数量：2
端子数量：14最高工作温度：85 °C
最低工作温度：-40 °C输出极性：COMPLEMENTARY
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP14,.3封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
Prop。Delay @ Nom-Sup：28 ns传播延迟（tpd）：28 ns
认证状态：Not Qualified座面最大高度：2 mm
子类别：FF/Latches最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：5.3 mm最小 fmax：100 MHz
Base Number Matches：1

SN74LV74DBLE 数据手册

 浏览型号SN74LV74DBLE的Datasheet PDF文件第2页浏览型号SN74LV74DBLE的Datasheet PDF文件第3页浏览型号SN74LV74DBLE的Datasheet PDF文件第4页浏览型号SN74LV74DBLE的Datasheet PDF文件第5页浏览型号SN74LV74DBLE的Datasheet PDF文件第6页浏览型号SN74LV74DBLE的Datasheet PDF文件第7页 
SN54LV74, SN74LV74  
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS  
SCLS189C – FEBRUARY 1993 – REVISED APRIL 1996  
SN54LV74 . . . J OR W PACKAGE  
SN74LV74 . . . D, DP, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) 2-µ Process  
Typical V (Output Ground Bounce)  
OLP  
< 0.8 V at V , T = 25°C  
CC  
A
1CLR  
1D  
V
CC  
2CLR  
2D  
1
2
3
4
5
6
7
14  
13  
12  
11  
Typical V  
> 2 V at V , T = 25°C  
(Output V  
Undershoot)  
OHV  
CC  
OH  
A
1CLK  
1PRE  
1Q  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model  
(C = 200 pF, R = 0)  
2CLK  
10 2PRE  
9
8
1Q  
2Q  
2Q  
GND  
Latch-Up Performance Exceeds 250 mA  
Per JEDEC Standard JESD-17  
SN54LV74 . . . FK PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW),  
Ceramic Flat (W) Packages, Chip Carriers  
(FK), and (J) 300-mil DIPs  
3
2
1
20 19  
18  
2D  
1CLK  
NC  
4
5
6
7
8
NC  
17  
16  
description  
2CLK  
1PRE  
NC  
15 NC  
14  
These dual positive-edge-triggered D-type flip-  
flops are designed for 2.7-V to 5.5-V V  
operation.  
2PRE  
1Q  
CC  
9 10 11 12 13  
A low level at the preset (PRE) or clear (CLR)  
inputs sets or resets the outputs regardless of the  
levels of the other inputs. When PRE and CLR are  
inactive (high), data at the data (D) inputs meeting  
the setup-time requirements is transferred to the  
NC – No internal connection  
outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly  
related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed  
without affecting the levels at the outputs.  
The SN74LV74 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count  
and functionality of standard small-outline packages in less than half the printed-circuit-board area.  
The SN54LV74 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74LV74 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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