SN74LV74DP

更新时间： 2024-11-19 23:03:19

品牌	Logo	应用领域
德州仪器 - TI		触发器
页数	文件大小	规格书
7页	139K
描述
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

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SN74LV74DP 数据手册

SN54LV74, SN74LV74

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

SCLS189C – FEBRUARY 1993 – REVISED APRIL 1996

SN54LV74 . . . J OR W PACKAGE

SN74LV74 . . . D, DP, OR PW PACKAGE

(TOP VIEW)

EPIC (Enhanced-Performance Implanted

CMOS) 2-µ Process

Typical V (Output Ground Bounce)

OLP

< 0.8 V at V , T = 25°C

1CLR

2CLR

Typical V

> 2 V at V , T = 25°C

(Output V

Undershoot)

OHV

1CLK

1PRE

ESD Protection Exceeds 2000 V Per

MIL-STD-883C, Method 3015; Exceeds

200 V Using Machine Model

(C = 200 pF, R = 0)

2CLK

10 2PRE

GND

Latch-Up Performance Exceeds 250 mA

Per JEDEC Standard JESD-17

SN54LV74 . . . FK PACKAGE

(TOP VIEW)

Package Options Include Plastic

Small-Outline (D), Shrink Small-Outline

(DB), Thin Shrink Small-Outline (PW),

Ceramic Flat (W) Packages, Chip Carriers

(FK), and (J) 300-mil DIPs

20 19

1CLK

description

2CLK

1PRE

15 NC

These dual positive-edge-triggered D-type flip-

flops are designed for 2.7-V to 5.5-V V

operation.

2PRE

9 10 11 12 13

A low level at the preset (PRE) or clear (CLR)

inputs sets or resets the outputs regardless of the

levels of the other inputs. When PRE and CLR are

inactive (high), data at the data (D) inputs meeting

the setup-time requirements is transferred to the

NC – No internal connection

outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly

related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed

without affecting the levels at the outputs.

The SN74LV74 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count

and functionality of standard small-outline packages in less than half the printed-circuit-board area.

The SN54LV74 is characterized for operation over the full military temperature range of –55°C to 125°C. The

SN74LV74 is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7

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与SN74LV74DP相关器件

型号	品牌	获取价格	描述	数据表
SN74LV74DR	ROCHESTER	获取价格	LV/LV-A/LVX/H SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO
SN74LV74DR	TI	获取价格	Dual Positive-Edge-Triggered D-Type Flip-Flop 14-SOIC -40 to 85
SN74LV74PW	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SN74LV74PWLE	TI	获取价格	暂无描述
SN74LV74PWR	TI	获取价格	暂无描述
SN74LV8151	TI	获取价格	10-BIT UNIVERSAL SCHMITT-TRIGGER BUFFER WITH 3-STATE OUTPUTS
SN74LV8151_07	TI	获取价格	10-BIT UNIVERSAL SCHMITT-TRIGGER BUFFER WITH 3-STATE OUTPUTS
SN74LV8151_08	TI	获取价格	10-BIT UNIVERSAL SCHMITT-TRIGGER BUFFER WITH 3-STATE OUTPUTS
SN74LV8151DGVR	TI	获取价格	10-BIT UNIVERSAL SCHMITT-TRIGGER BUFFER WITH 3-STATE OUTPUTS
SN74LV8151DGVRE4	TI	获取价格	10-BIT UNIVERSAL SCHMITT-TRIGGER BUFFER WITH 3-STATE OUTPUTS

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