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SN74ALVCH16652DGGR PDF预览

SN74ALVCH16652DGGR

更新时间： 2024-09-16 15:52:07
品牌 Logo 应用领域
德州仪器 - TI 输入元件光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
11页 518K
描述
ALVC/VCX/A SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, PLASTIC, TSSOP-56

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SN74ALVCH16652DGGR 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP56,.3,20
针数：56Reach Compliance Code：not_compliant
风险等级：5.92其他特性：SELECT INPUT FOR MULTIPLEXED TRANSMISSION OF REGISTERED/REAL TIME DATA
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G56
长度：14 mm逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
最大I（ol）：0.024 A位数：8
功能数量：2端口数量：2
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP56,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A触发器类型：POSITIVE EDGE
宽度：6.1 mmBase Number Matches：1

SN74ALVCH16652DGGR 数据手册

 浏览型号SN74ALVCH16652DGGR的Datasheet PDF文件第2页浏览型号SN74ALVCH16652DGGR的Datasheet PDF文件第3页浏览型号SN74ALVCH16652DGGR的Datasheet PDF文件第4页浏览型号SN74ALVCH16652DGGR的Datasheet PDF文件第5页浏览型号SN74ALVCH16652DGGR的Datasheet PDF文件第6页浏览型号SN74ALVCH16652DGGR的Datasheet PDF文件第7页 
SN74ALVCH16652  
16-BIT BUS TRANSCEIVER AND REGISTER  
WITH 3-STATE OUTPUTS  
SCES034A – JULY 1995 – REVISED FEBRUARY 1999  
DGG OR DL PACKAGE  
(TOP VIEW)  
D
D
D
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
1OEAB  
1CLKAB  
1SAB  
GND  
1OEBA  
1CLKBA  
1SBA  
GND  
2
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
3
4
5
1A1  
1B1  
D
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
6
1A2  
1B2  
7
V
V
CC  
CC  
8
1A3  
1A4  
1A5  
GND  
1A6  
1A7  
1A8  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
1B3  
1B4  
1B5  
GND  
1B6  
1B7  
1B8  
2B1  
2B2  
2B3  
GND  
2B4  
2B5  
2B6  
9
description  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
This 16-bit bus transceiver and register is  
designed for 1.65-V to 3.6-V V operation.  
CC  
The SN74ALVCH16652 consists of D-type  
flip-flops and control circuitry arranged for  
multiplexed transmission of data directly from the  
data bus or from the internal storage registers.  
The device can be used as two 8-bit transceivers  
or one 16-bit transceiver.  
Complementary output-enable (OEAB and  
OEBA) inputs are provided to control the  
transceiver functions. Select-control (SAB and  
SBA) inputs are provided to select whether  
real-time or stored data is transferred. A low input  
level selects real-time data, and a high input level  
selects stored data. The circuitry used for select  
control eliminates the typical decoding glitch that  
occurs in a multiplexer during the transition  
between stored and real-time data. Figure 1  
illustrates the four fundamental bus-management  
functions that can be performed with the  
SN74ALVCH16652.  
V
V
CC  
CC  
2A7  
2A8  
GND  
2SAB  
2B7  
2B8  
GND  
2SBA  
2CLKBA  
2OEBA  
2CLKAB  
2OEAB  
Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the  
appropriate clock (CLKAB or CLKBA) inputs regardless of the levels on the select-control or output-enable  
inputs. When SAB and SBA are in the real-time transfer mode, it also is possible to store data without using the  
internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output  
reinforces its input. Thus, when all other data sources to the two sets of bus line are in the high-impedance state,  
each set of bus lines remains at its last level configuration.  
Active bus-hold circuitry is provided to hold unused for floating inputs at a valid logic level.  
To ensure the high-impedance state during power up or power down, OEBA should be tied to V  
through a  
CC  
pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor  
is determined by the current-sinking current-sourcing capability of the driver.  
The SN74ALVCH16652 is characterized for operation from –40°C to 85°C.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
3–251  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

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SN74ALVCH16652DL TI

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 		ALVC/VCX/A SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 0.300 INCH, PLA
SN74ALVCH16721 TI

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 		3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
SN74ALVCH16721DGG TI

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 		3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
SN74ALVCH16721DGGR TI

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 		具有三态输出的 3.3V 20 位触发器 | DGG | 56 | -40 to 85
SN74ALVCH16721DGV TI

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 		3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
SN74ALVCH16721DL TI

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 		3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
SN74ALVCH16721DLR TI

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 		具有三态输出的 3.3V 20 位触发器 | DL | 56 | -40 to 85
SN74ALVCH16820 TI

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 		3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS AND 3-STATE OUTPUTS
SN74ALVCH16820DGG TI

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 		3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS AND 3-STATE OUTPUTS
SN74ALVCH16820DGGR ROCHESTER

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 		ALVC/VCX/A SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, TSSOP-56

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