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SN74ALVCH16721DGV PDF预览

SN74ALVCH16721DGV

更新时间： 2024-11-05 23:09:43
品牌 Logo 应用领域
德州仪器 - TI 触发器输出元件
页数 文件大小 规格书
9页 139K
描述
3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS

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SN74ALVCH16721DGV 技术参数

生命周期：Obsolete零件包装代码：SSOP
包装说明：TSSOP, TSSOP56,.25,16针数：56
Reach Compliance Code：unknown风险等级：5.58
其他特性：WITH CLOCK ENABLE系列：ALVC/VCX/A
JESD-30 代码：R-PDSO-G56长度：11.3 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大频率@ Nom-Sup：150000000 Hz最大I（ol）：0.024 A
位数：20功能数量：1
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP56,.25,16封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH电源：3.3 V
Prop。Delay @ Nom-Sup：4.3 ns传播延迟（tpd）：5.6 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：FF/Latches最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.4 mm端子位置：DUAL
触发器类型：POSITIVE EDGE宽度：4.4 mm
Base Number Matches：1

SN74ALVCH16721DGV 数据手册

 浏览型号SN74ALVCH16721DGV的Datasheet PDF文件第2页浏览型号SN74ALVCH16721DGV的Datasheet PDF文件第3页浏览型号SN74ALVCH16721DGV的Datasheet PDF文件第4页浏览型号SN74ALVCH16721DGV的Datasheet PDF文件第5页浏览型号SN74ALVCH16721DGV的Datasheet PDF文件第6页浏览型号SN74ALVCH16721DGV的Datasheet PDF文件第7页 
SN74ALVCH16721  
3.3-V 20-BIT FLIP-FLOP  
WITH 3-STATE OUTPUTS  
SCES052D – JULY 1995 – REVISED FEBRUARY 1999  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
OE  
Q1  
Q2  
GND  
Q3  
Q4  
1
2
3
4
5
6
7
8
9
56 CLK  
55 D1  
54 D2  
53 GND  
52 D3  
51 D4  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
V
50  
V
CC  
CC  
Q5  
Q6  
Q7 10  
GND 11  
Q8 12  
49 D5  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
48 D6  
47 D7  
46 GND  
45 D8  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL), Thin Shrink  
Small-Outline (DGG), and Thin Very  
Small-Outline (DGV) Packages  
Q9 13  
44 D9  
Q10 14  
Q11 15  
Q12 16  
Q13 17  
GND 18  
Q14 19  
Q15 20  
Q16 21  
43 D10  
42 D11  
41 D12  
40 D13  
39 GND  
38 D14  
37 D15  
36 D16  
description  
This 20-bit flip-flop is designed specifically for  
1.65-V to 3.6-V V operation.  
CC  
The 20 flip-flops of the SN74ALVCH16721 are  
edge-triggered D-type flip-flops with qualified  
clock storage. On the positive transition of the  
clock (CLK) input, the device provides true data at  
the Q outputs if the clock-enable (CLKEN) input is  
low. If CLKEN is high, no data is stored.  
V
22  
35  
V
CC  
CC  
Q17 23  
34 D17  
24  
25  
26  
27  
28  
33  
32  
31  
30  
29  
Q18  
GND  
Q19  
Q20  
NC  
D18  
GND  
D19  
D20  
CLKEN  
A buffered output-enable (OE) input places the  
20 outputs in either a normal logic state (high or  
low) or the high-impedance state. In the  
high-impedance state, the outputs neither load  
nor drive the bus lines significantly. The  
high-impedance state and increased drive  
provide the capability to drive bus lines without  
need for interface or pullup components. OE does  
not affect the internal operation of the flip-flops.  
Old data can be retained or new data can be  
entered while the outputs are in the  
high-impedance state.  
NC – No internal connection  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVCH16721 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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与SN74ALVCH16721DGV相关器件

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SN74ALVCH16721DL TI

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 		3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
SN74ALVCH16721DLR TI

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 		具有三态输出的 3.3V 20 位触发器 | DL | 56 | -40 to 85
SN74ALVCH16820 TI

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 		3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS AND 3-STATE OUTPUTS
SN74ALVCH16820DGG TI

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 		3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS AND 3-STATE OUTPUTS
SN74ALVCH16820DGGR ROCHESTER

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 		ALVC/VCX/A SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, TSSOP-56
SN74ALVCH16820DGGR TI

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 		3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS AND 3-STATE OUTPUTS
SN74ALVCH16820DL TI

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 		3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS AND 3-STATE OUTPUTS
SN74ALVCH16820DL ROCHESTER

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 		ALVC/VCX/A SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, SSOP-56
SN74ALVCH16821 TI

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 		3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74ALVCH16821_08 TI

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 		3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

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