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SN74ALVCH16827 PDF预览

SN74ALVCH16827

更新时间： 2024-11-03 23:09:43
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器输出元件
页数 文件大小 规格书
9页 124K
描述
20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS

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SN74ALVCH16827 技术参数

生命周期：Obsolete包装说明：,
Reach Compliance Code：unknown风险等级：5.73
Base Number Matches：1

SN74ALVCH16827 数据手册

 浏览型号SN74ALVCH16827的Datasheet PDF文件第2页浏览型号SN74ALVCH16827的Datasheet PDF文件第3页浏览型号SN74ALVCH16827的Datasheet PDF文件第4页浏览型号SN74ALVCH16827的Datasheet PDF文件第5页浏览型号SN74ALVCH16827的Datasheet PDF文件第6页浏览型号SN74ALVCH16827的Datasheet PDF文件第7页 
SN74ALVCH16827  
20-BIT BUFFER/DRIVER  
WITH 3-STATE OUTPUTS  
SCES041C – JULY 1995 – REVISED FEBRUARY 1999  
DGG OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
1OE1  
1Y1  
1Y2  
GND  
1Y3  
1Y4  
1OE2  
1A1  
1A2  
GND  
1A3  
1A4  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
2
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
3
4
5
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
6
V
V
7
CC  
CC  
1Y5  
1Y6  
1Y7  
GND  
1Y8  
1A5  
1A6  
1A7  
GND  
1A8  
8
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
9
10  
11  
12  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
1Y9 13  
1Y10 14  
2Y1 15  
2Y2 16  
2Y3 17  
GND 18  
2Y4 19  
2Y5 20  
2Y6 21  
44 1A9  
43 1A10  
42 2A1  
41 2A2  
40 2A3  
39 GND  
38 2A4  
37 2A5  
36 2A6  
description  
This 20-bit noninverting buffer/driver is designed  
for 1.65-V to 3.6-V V operation.  
CC  
TheSN74ALVCH16827iscomposedoftwo10-bit  
sections with separate output-enable signals. For  
either 10-bit buffer section, the two output-enable  
(1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must  
both be low for the corresponding Y outputs to be  
active. If either output-enable input is high, the  
outputs of that 10-bit buffer section are in the  
high-impedance state.  
V
22  
35  
V
CC  
CC  
2Y7 23  
34 2A7  
33 2A8  
2Y8 24  
GND  
25  
32  
GND  
31 2A9  
2Y9 26  
2Y10 27  
2OE1 28  
30 2A10  
29 2OE2  
To ensure the high-impedance state during power  
up or power down, OE should be tied to V  
CC  
through a pullup resistor; the minimum value of  
the resistor is determined by the current-sinking  
capability of the driver.  
Active bus-hold circuitry is provided to hold  
unused or floating data inputs at a valid logic level.  
The SN74ALVCH16827 is characterized for  
operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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