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SN74ALVCH16821_08

更新时间： 2024-11-19 05:29:35
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德州仪器 - TI 触发器输出元件
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12页 312K
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3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

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SN74ALVCH16821_08 数据手册

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SN74ALVCH16821  
3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES037F–JULY 1995–REVISED SEPTEMBER 2004  
FEATURES  
DGG OR DL PACKAGE  
(TOP VIEW)  
•
•
•
•
Member of the Texas Instruments Widebus™  
Family  
1
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
1CLK  
1D1  
1D2  
GND  
1D3  
1D4  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
2
3
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
4
5
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
6
7
V
CC  
V
CC  
8
1Q5  
1Q6  
1Q7  
GND  
1Q8  
1Q9  
1Q10  
2Q1  
2Q2  
2Q3  
GND  
2Q4  
2Q5  
2Q6  
1D5  
1D6  
1D7  
GND  
1D8  
1D9  
1D10  
2D1  
2D2  
2D3  
GND  
2D4  
2D5  
2D6  
9
DESCRIPTION/ORDERING INFORMATION  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
This 20-bit bus-interface flip-flop is designed for  
1.65-V to 3.6-V VCC operation.  
The SN74ALVCH16821 can be used as two 10-bit  
flip-flops or one 20-bit flip-flop. The 20 flip-flops are  
edge-triggered D-type flip-flops. On the positive  
transition of the clock (CLK) input, the device  
provides true data at the Q outputs.  
A buffered output-enable (OE) input can be used to  
place the ten outputs in either a normal logic state  
(high or low logic levels) or the high-impedance state.  
In the high-impedance state, the outputs neither load  
nor drive the bus lines significantly. The  
high-impedance state and increased drive provide the  
capability to drive bus lines without need for interface  
or pullup components.  
V
CC  
V
CC  
2Q7  
2Q8  
2D7  
2D8  
GND  
2Q9  
2Q10  
2OE  
GND  
2D9  
2D10  
2CLK  
OE does not affect the internal operation of the  
flip-flops. Old data can be retained or new data can  
be entered while the outputs are in the  
high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors  
with the bus-hold circuitry is not recommended.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74ALVCH16821DL  
TOP-SIDE MARKING  
ALVCH16821  
ALVCH16821  
Tube  
SSOP - DL  
TSSOP - DGG  
-40°C to 85°C  
Tape and reel  
Tape and reel  
SN74ALVCH16821DLR  
SN74ALVCH16821DGGR  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1995–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...12

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 		3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74ALVCH16821DL TI

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 		3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74ALVCH16821DLR TI

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SN74ALVCH16823 TI

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SN74ALVCH16823DGG TI

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 		18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74ALVCH16823DGGR TI

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 		具有三态输出的 18 位总线接口触发器 | DGG | 56 | -40 to 85
SN74ALVCH16823DGVR TI

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 		具有三态输出的 18 位总线接口触发器 | DGV | 56 | -40 to 85
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 		18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74ALVCH16823DLG4 TI

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