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SN74ALVCH16721 PDF预览

SN74ALVCH16721

更新时间： 2024-11-08 23:09:43
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德州仪器 - TI 触发器输出元件
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3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS

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SN74ALVCH16721 数据手册

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SN74ALVCH16721  
3.3-V 20-BIT FLIP-FLOP  
WITH 3-STATE OUTPUTS  
SCES052D – JULY 1995 – REVISED FEBRUARY 1999  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
OE  
Q1  
Q2  
GND  
Q3  
Q4  
1
2
3
4
5
6
7
8
9
56 CLK  
55 D1  
54 D2  
53 GND  
52 D3  
51 D4  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
V
50  
V
CC  
CC  
Q5  
Q6  
Q7 10  
GND 11  
Q8 12  
49 D5  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
48 D6  
47 D7  
46 GND  
45 D8  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL), Thin Shrink  
Small-Outline (DGG), and Thin Very  
Small-Outline (DGV) Packages  
Q9 13  
44 D9  
Q10 14  
Q11 15  
Q12 16  
Q13 17  
GND 18  
Q14 19  
Q15 20  
Q16 21  
43 D10  
42 D11  
41 D12  
40 D13  
39 GND  
38 D14  
37 D15  
36 D16  
description  
This 20-bit flip-flop is designed specifically for  
1.65-V to 3.6-V V operation.  
CC  
The 20 flip-flops of the SN74ALVCH16721 are  
edge-triggered D-type flip-flops with qualified  
clock storage. On the positive transition of the  
clock (CLK) input, the device provides true data at  
the Q outputs if the clock-enable (CLKEN) input is  
low. If CLKEN is high, no data is stored.  
V
22  
35  
V
CC  
CC  
Q17 23  
34 D17  
24  
25  
26  
27  
28  
33  
32  
31  
30  
29  
Q18  
GND  
Q19  
Q20  
NC  
D18  
GND  
D19  
D20  
CLKEN  
A buffered output-enable (OE) input places the  
20 outputs in either a normal logic state (high or  
low) or the high-impedance state. In the  
high-impedance state, the outputs neither load  
nor drive the bus lines significantly. The  
high-impedance state and increased drive  
provide the capability to drive bus lines without  
need for interface or pullup components. OE does  
not affect the internal operation of the flip-flops.  
Old data can be retained or new data can be  
entered while the outputs are in the  
high-impedance state.  
NC – No internal connection  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVCH16721 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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