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SI5326A-B-GMR

更新时间: 2024-11-23 12:59:19
品牌 Logo 应用领域
芯科 - SILICON 衰减器时钟
页数 文件大小 规格书
16页 619K
描述
Processor Specific Clock Generator, 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD, QFN-36

SI5326A-B-GMR 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:QFN包装说明:HVQCCN,
针数:36Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.76
Is Samacsys:NJESD-30 代码:S-XQCC-N36
长度:6 mm端子数量:36
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:0.9 mm表面贴装:YES
温度等级:INDUSTRIAL端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

SI5326A-B-GMR 数据手册

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Si5326  
PRELIMINARY DATA SHEET  
ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR  
Description  
Features  
The Si5326 is a jitter-attenuating precision clock multiplier for  
applications requiring sub 1 ps jitter performance. The Si5326  
accepts dual clock inputs ranging from 2 kHz to 710 MHz and  
generates two clock outputs ranging from 2 kHz to 945 MHz  
and select frequencies to 1.4 GHz. The two outputs are  
divided down separately from a common source. The device  
provides virtually any frequency translation combination  
across this operating range. The Si5326 input clock  
frequency and clock multiplication ratio are programmable  
through an I2C or SPI interface. The Si5326 is based on  
Silicon Laboratories' 3rd-generation DSPLL® technology,  
which provides any-rate frequency synthesis and jitter  
attenuation in a highly integrated PLL solution that eliminates  
the need for external VCXO and loop filter components. The  
DSPLL loop bandwidth is digitally programmable, providing  
jitter performance optimization at the application level.  
Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5326  
is ideal for providing clock multiplication and jitter attenuation  
in high performance timing applications.  
Generates any frequency from 2 kHz to 945 MHz  
and select frequencies to 1.4 GHz from an input  
frequency of 2 kHz to 710 MHz  
Ultra-low jitter clock outputs w/jitter generation as  
low as 0.3 ps rms (50 kHz–80 MHz)  
Integrated loop filter with selectable loop bandwidth  
(60 Hz to 8.4 kHz)  
Meets OC-192 GR-253-CORE jitter specifications  
Dual clock inputs w/manual or automatically  
controlled hitless switching  
Dual clock outputs with selectable signal format  
(LVPECL, LVDS, CML, CMOS)  
Support for ITU G.709 and custom FEC ratios  
(255/238, 255/237, 255/236)  
LOL, LOS, FOS alarm outputs  
Digitally-controlled output phase adjust  
2
I C or SPI programmable  
Applications  
On-chip voltage regulator for 1.8, 2.5, or 3.3 V  
SONET/SDH OC-48/OC-192 line cards  
GbE/10GbE, 1/2/4/8/10GFC line cards  
ITU G.709 and custom FEC line cards  
Optical modules  
Wireless basestations  
Data converter clocking  
±10% operation  
Small size: 6 x 6 mm 36-lead QFN  
Pb-free, ROHS compliant  
xDSL  
SONET/SDH + PDH clock synthesis  
Test and measurement  
Xtal or Refclock  
÷ N31  
÷ N32  
CKIN1  
CKIN2  
÷ NC1  
÷ NC2  
CKOUT1  
CKOUT2  
®
DSPLL  
÷ N2  
Loss of Signal/  
Frequency Offset  
VDD (1.8, 2.5, or 3.3 V)  
GND  
Control  
Signal Detect  
Loss of Lock  
I2C/SPI Port  
Clock Select  
Latency Control  
Device Interrupt  
Rate Select  
Confidential Rev. 0.2 2/07  
Copyright © 2007 by Silicon Laboratories  
Si5326  
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.  

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