Datasheet > SI5330

SI5330

更新时间： 2024-11-19 12:04:39

品牌	Logo	应用领域
芯科 - SILICON		时钟
页数	文件大小	规格书
20页	158K
描述
Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs

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中文翻译

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数据手册

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SI5330 数据手册

Si5330

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW

CLOCK BUFFER/LEVEL TRANSLATOR

Features

 Supports single-ended or

 Output-output skew: 100 ps

 Propagation delay: 2.5 ns typ

differential input clock signals

 Generates four differential

(LVPECL, LVDS, HCSL) or eight

single-ended (CMOS, SSTL,

HSTL) outputs

 Single core supply with excellent

PSRR: 1.8, 2.5, or 3.3 V

 Output driver supply voltage

independent of core supply: 1.5,

1.8, 2.5, or 3.3 V

 Provides signal level translation

Differential to single-ended

Single-ended to differential

Differential to differential

Single-ended to single-ended

 Wide frequency range

 Loss of Signal (LOS) indicator

Ordering Information:

allows system clock monitoring

See page 14.

 Output Enable (OEB) pin allows

glitchless control of output clocks

 Low power: 10 mA typical core

Pin Assignments

LVPECL, LVDS: 5 to 710 MHz

HCSL: 5 to 250 MHz

SSTL, HSTL: 5 to 350 MHz

CMOS: 5 to 200 MHz

current

 Industrial temperature range:

–40 to +85 C

 Small size: 24-lead, 4 x 4 mm

 Additive jitter: 150 fs RMS typ

QFN

CLK1A

CLK1B

VDDO1

IN1

IN2

Applications

IN3

GND

 High Speed Clock Distribution

 Ethernet Switch/Router

 SONET / SDH

 PCI Express 2.0/3.0

 Fibre Channel

 MSAN/DSLAM/PON

 Telecom Line Cards

RSVD_GND

VDDO2

CLK2A

RSVD_GND

CLK2B

Functional Block Diagram

V_DD

V_DDO0

CLK0

Si5330

V_DDO1

CLK1

Single-ended

Differential

V_DDO2

CLK2

Differential

V_DDO3

CLK3

LOS

Control

OEB

Rev. 1.0 4/12

Si5330

12 3 4 5 6 7...20

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