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SI5328B-C-GMR PDF预览

SI5328B-C-GMR

更新时间: 2024-11-19 20:10:59
品牌 Logo 应用领域
芯科 - SILICON ATM异步传输模式电信电信集成电路
页数 文件大小 规格书
70页 1864K
描述
Support Circuit, 1-Func, 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD, QFN-36

SI5328B-C-GMR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:6 X 6 MM, ROHS COMPLIANT, MO-220VJJD, QFN-36
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:1.79Samacsys Description:ic
JESD-30 代码:S-XQCC-N36长度:6 mm
功能数量:1端子数量:36
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED座面最大高度:0.9 mm
标称供电电压:2.5 V表面贴装:YES
电信集成电路类型:ATM/SONET/SDH SUPPORT CIRCUIT温度等级:INDUSTRIAL
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:6 mmBase Number Matches:1

SI5328B-C-GMR 数据手册

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Si5328  
ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING  
CLOCK MULTIPLIER  
Features  
Fully-compliant with ITU-T  
Dual clock outputs with  
selectable signal format  
G.8262, EEC options 1 and 2.  
(LVPECL, LVDS, CML, CMOS)  
Generates any frequency from  
8 kHz to 808 MHz.  
LOL, LOS, FOS alarm outputs  
2
Ultra-low jitter clock outputs with  
jitter generation as low as 0.3 ps  
rms (12 kHz–20 MHz)  
I C or SPI programmable  
On-chip voltage regulator for  
2.5 ±10% or 3.3 V ±10%  
operation  
Integrated loop filter with  
selectable loop bandwidth  
(0.1 Hz; 1 to 10 Hz)  
Ordering Information:  
Small size: 6 x 6 mm 36-lead  
See page 63.  
QFN  
Dual clock inputs with manual or  
automatically controlled hitless  
switching  
Pb-free, ROHS compliant  
Pin Assignments  
Applications  
G.8262 Synchronous Ethernet, Carrier Ethernet switches,  
36 35 34 33 32 31 30 29 28  
EEC options 1 and 2  
routers  
RST  
NC  
1
2
3
4
5
6
7
8
9
27 SDI  
26  
A2_SS  
25 A1  
GbE/10GbE/100GbE  
INT_C1B  
C2B  
Synchronous Ethernet  
24  
23  
A0  
GND  
Pad  
VDD  
XA  
SDA_SDO  
22 SCL  
Description  
XB  
21  
20  
CS_CA  
NC  
GND  
NC  
19 NC  
The Si5328 is a jitter-attenuating precision clock multiplier for  
Synchronous Ethernet applications requiring sub 1 ps jitter performance  
and ultra-low loop bandwidth. When combined with a low-wander, low-  
jitter reference oscillator, the Si5328 meets all of the wander, MTIE,  
TDEV, and other requirements listed in ITU-T G.8262/Y.1362. The Si5328  
accepts two input clocks ranging from 8 kHz to 710 MHz and generates  
two output clocks ranging from 8 kHz to 808 MHz. The two outputs are  
divided down separately from a common source. The Si5328 can also  
use the TCXO as a clock source for frequency synthesis. The device  
provides virtually any frequency translation combination across this  
operating range. The Si5328 input clock frequency and clock  
10 11 12 13 14 15 16 17 18  
2
multiplication ratio are programmable through an I C or SPI interface. The  
®
Si5328 is based on Silicon Laboratories' third-generation DSPLL  
technology, which provides frequency synthesis and jitter attenuation in a  
highly integrated PLL solution that eliminates the need for external VCXO  
and loop filter components. The DSPLL loop bandwidth is digitally  
programmable, providing jitter performance optimization at the application  
level. Operating from a single 2.5 or 3.3 V supply, the Si5328 is ideal for  
providing clock multiplication and jitter attenuation in high-performance,  
Synchronous Ethernet timing applications.  
Rev. 1.0 7/13  
Copyright © 2013 by Silicon Laboratories  
Si5328  

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