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Si5328-EVB

更新时间： 2024-11-19 12:46:59

品牌	Logo	应用领域
芯科 - SILICON		以太网以太网：16GBASE-T 时钟
页数	文件大小	规格书
70页	427K
描述
ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

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Si5328-EVB 数据手册

Si5328

ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING

CLOCK MULTIPLIER

Features

 Fully-compliant with ITU-T

 Dual clock outputs with

selectable signal format

G.8262, EEC options 1 and 2.

(LVPECL, LVDS, CML, CMOS)

 Generates any frequency from

8 kHz to 808 MHz.

 LOL, LOS, FOS alarm outputs

 Ultra-low jitter clock outputs with

jitter generation as low as 0.3 ps

rms (12 kHz–20 MHz)

 I C or SPI programmable

 On-chip voltage regulator for

2.5 ±10% or 3.3 V ±10%

operation

 Integrated loop filter with

selectable loop bandwidth

(0.1 Hz; 1 to 10 Hz)

Ordering Information:

 Small size: 6 x 6 mm 36-lead

See page 63.

QFN

 Dual clock inputs with manual or

automatically controlled hitless

switching

 Pb-free, ROHS compliant

Pin Assignments

Applications

 G.8262 Synchronous Ethernet,  Carrier Ethernet switches,

36 35 34 33 32 31 30 29 28

EEC options 1 and 2

routers

RST

27 SDI

A2_SS

25 A1

 GbE/10GbE/100GbE

INT_C1B

C2B

Synchronous Ethernet

GND

Pad

VDD

SDA_SDO

22 SCL

Description

CS_CA

GND

19 NC

The Si5328 is a jitter-attenuating precision clock multiplier for

Synchronous Ethernet applications requiring sub 1 ps jitter performance

and ultra-low loop bandwidth. When combined with a low-wander, low-

jitter reference oscillator, the Si5328 meets all of the wander, MTIE,

TDEV, and other requirements listed in ITU-T G.8262/Y.1362. The Si5328

accepts two input clocks ranging from 8 kHz to 710 MHz and generates

two output clocks ranging from 8 kHz to 808 MHz. The two outputs are

divided down separately from a common source. The Si5328 can also

use the TCXO as a clock source for frequency synthesis. The device

provides virtually any frequency translation combination across this

operating range. The Si5328 input clock frequency and clock

10 11 12 13 14 15 16 17 18

multiplication ratio are programmable through an I C or SPI interface. The

Si5328 is based on Silicon Laboratories' third-generation DSPLL

technology, which provides frequency synthesis and jitter attenuation in a

highly integrated PLL solution that eliminates the need for external VCXO

and loop filter components. The DSPLL loop bandwidth is digitally

programmable, providing jitter performance optimization at the application

level. Operating from a single 2.5 or 3.3 V supply, the Si5328 is ideal for

providing clock multiplication and jitter attenuation in high-performance,

Synchronous Ethernet timing applications.

Rev. 1.0 7/13

Si5328

12 3 4 5 6 7...70

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与Si5328-EVB相关器件

型号	品牌	获取价格	描述	数据表
SI533	SILICON	获取价格	DUAL FREQUENCY CRYSTAL OSCILLATOR (XO) (10 MHZ TO 1.4 GHZ)
SI5330	SILICON	获取价格	Supports single-ended or differential input clock singnals Generates four differential (LV
SI53301-B-GM	SILICON	获取价格	Interface Circuit, CMOS, 5 X 5 MM, ROHS COMPLIANT, MO-220, QFN-32
SI53302-B-GM	SILICON	获取价格	Interface Circuit, CMOS, 7 X 7 MM, ROHS COMPLIANT, MO-220, QFN-44
SI53304-B-GM	SILICON	获取价格	Interface Circuit, 5 X 5 MM, ROHS COMPLIANT, MO-220, QFN-32
SI53305-B-GM	SILICON	获取价格	Interface Circuit, QFN-44
SI53305-B-GMR	SILICON	获取价格	Clock Driver
SI53307-B-GM	SILICON	获取价格	Low Skew Clock Driver, 53307 Series, 4 True Output(s), 0 Inverted Output(s), CMOS, 3 X 3 M
SI53307-B-GMR	SILICON	获取价格	IC CLK BUFFER 2:4 725MHZ 16QFN
SI53308-B-GM	SILICON	获取价格	Low Skew Clock Driver, 53308 Series, 6 True Output(s), 0 Inverted Output(s), CMOS, 5 X 5 M

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