Datasheet > SI53305-B-GMR

SI53305-B-GMR

更新时间： 2024-11-19 21:14:11

品牌	Logo	应用领域
芯科 - SILICON		驱动逻辑集成电路
页数	文件大小	规格书
36页	1777K
描述
Clock Driver

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中文翻译

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技术参数
数据手册

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SI53305-B-GMR 技术参数

是否Rohs认证：	符合	生命周期：	Active
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	1.76	逻辑集成电路类型：	LOW SKEW CLOCK DRIVER
Base Number Matches：	1

SI53305-B-GMR 数据手册

Si53305

1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL

TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE

Features



10 differential or 20 LVCMOS outputs Low output-output skew: <70 ps

Ultra-low additive jitter: 45 fs rms

Wide frequency range:



Low propagation delay variation:

<400 ps

dc to 725 MHz



Independent V_DDand V_DDO

1.8/2.5/3.3 V

Excellent power supply noise

rejection (PSRR)

Selectable LVCMOS drive strength to

tailor jitter and EMI performance

Small size: 44-QFN (7 mm x 7 mm)

RoHS compliant, Pb-free

Industrial temperature range:

–40 to +85 °C



Any-format input with pin selectable

output formats: LVPECL, Low Power

LVPECL, LVDS, CML, HCSL,

LVCMOS

2:1 mux with hot-swappable inputs

Glitchless input clock switching

(1 MHz to 725 MHz)



Ordering Information:



Individual output enable

Synchronous output enable

See page 30.

Applications

Pin Assignments

Si53305



High-speed clock distribution

Ethernet switch/router

Optical Transport Network (OTN)

SONET/SDH



Storage

Telecom

Industrial

Servers

PCI Express Gen 1/2/3

Backplane clock distribution

OE₂

OE₇

SFOUT[0]

SFOUT[1]

Description

OE₁

OE₈

GND

PAD

The Si53305 is an ultra low jitter ten output differential buffer with pin-selectable

output clock signal format and individual OE. The Si53305 features a 2:1 mux with

glitchless switching, making it ideal for redundant clocking applications. The

Si53305 utilizes Silicon Laboratories' advanced CMOS technology to fanout

clocks from dc to 725 MHz with guaranteed low additive jitter, low skew, and low

propagation delay variability. The Si53305 features minimal cross-talk and

provides superior supply noise rejection, simplifying low jitter clock distribution in

noisy environments. Independent core and output bank supply pins provide

integrated level translation without the need for external circuitry.

GND

OE₉

OE₀

Patents pending

Functional Block Diagram

Power

Vref

Supply

V_REF

Generator

Filtering

VDDO_A

OE[0:4]

Q0, Q1, Q2, Q3, Q4

CLK0

SFOUT[1:0]

VDDO_B

CLK1

OE[5:9]

Q5, Q6, Q7, Q8, Q9

Switching

Logic

Q5, Q6, Q7, Q8, Q9

CLK_SEL

Rev. 1.0 9/15

Si53305

12 3 4 5 6 7...36

中文翻译

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与SI53305-B-GMR相关器件

型号	品牌	获取价格	描述	数据表
SI53307-B-GM	SILICON	获取价格	Low Skew Clock Driver, 53307 Series, 4 True Output(s), 0 Inverted Output(s), CMOS, 3 X 3 M
SI53307-B-GMR	SILICON	获取价格	IC CLK BUFFER 2:4 725MHZ 16QFN
SI53308-B-GM	SILICON	获取价格	Low Skew Clock Driver, 53308 Series, 6 True Output(s), 0 Inverted Output(s), CMOS, 5 X 5 M
SI5330A-A00200-GM	SILICON	获取价格	Supports single-ended or differential input clock singnals Generates four differential (LV
SI5330A-A00200-GMR	SILICON	获取价格	Clock Driver
SI5330A-A00202-GM	SILICON	获取价格	1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR
SI5330A-B00200-GM	SILICON	获取价格	Low Skew Clock Driver, 5330 Series, 4 True Output(s), 0 Inverted Output(s), 4 X 4 MM, ROHS
SI5330A-B00202-GM	SILICON	获取价格	Low Skew Clock Driver, 5330 Series, 4 True Output(s), 0 Inverted Output(s), QFN-24
SI5330B-A00204-GM	SILICON	获取价格	Supports single-ended or differential input clock singnals Generates four differential (LV
SI5330B-A00204-GMR	SILICON	获取价格	Clock Driver

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