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SI5327B-C-GM PDF预览

SI5327B-C-GM

更新时间: 2024-11-19 15:51:11
品牌 Logo 应用领域
芯科 - SILICON 时钟外围集成电路晶体
页数 文件大小 规格书
60页 1942K
描述
Processor Specific Clock Generator, 808MHz, CMOS, QFN-36

SI5327B-C-GM 技术参数

是否Rohs认证:符合生命周期:Active
零件包装代码:QFN包装说明:HVQCCN, LCC36,.25SQ,20
针数:36Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:2.29Is Samacsys:N
其他特性:CAN ALSO OPERATE AT 2.5V AND 3.3V SUPPLYJESD-30 代码:S-XQCC-N36
长度:6 mm端子数量:36
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:808 MHz封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装等效代码:LCC36,.25SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED电源:1.8/3.3 V
主时钟/晶体标称频率:710 MHz认证状态:Not Qualified
座面最大高度:0.9 mm子类别:Clock Generators
最大压摆率:279 mA最大供电电压:1.89 V
最小供电电压:1.71 V标称供电电压:1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

SI5327B-C-GM 数据手册

 浏览型号SI5327B-C-GM的Datasheet PDF文件第2页浏览型号SI5327B-C-GM的Datasheet PDF文件第3页浏览型号SI5327B-C-GM的Datasheet PDF文件第4页浏览型号SI5327B-C-GM的Datasheet PDF文件第5页浏览型号SI5327B-C-GM的Datasheet PDF文件第6页浏览型号SI5327B-C-GM的Datasheet PDF文件第7页 
Si5327  
ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER  
ATTENUATOR  
Features  
Generates any frequency from 2 kHz Dual clock inputs with manually  
to 808 MHz from an input frequency  
of 2 kHz to 710 MHz  
controlled hitless switching  
Free run and VCO freeze modes  
Ultra-low jitter clock outputs with jitter Support for ITU G.709 and custom  
generation as low as 0.5 ps rms  
(12 kHz–20 MHz)  
FEC ratios (255/238, 255/237,  
255/236)  
Integrated loop filter with selectable  
loop bandwidth (4 to 525 Hz)  
Meets OC-192 GR-253-CORE jitter  
specifications  
LOL and LOS alarm outputs  
I2C or SPI programmable  
Single 1.8, 2.5, 3.3 V supply  
Small size: 6 x 6 mm 36-lead QFN  
Pb-free, ROHS compliant  
Ordering Information:  
See page 54.  
Applications  
Dual clock outputs with  
programmable signal format  
(LVPECL, LVDS, CML, CMOS)  
SONET/SDH OC-48/OC-192/STM-  
16/STM-64 line cards  
ITU G.709 and custom FEC line  
cards  
GbE/10GbE, 1/2/4/8/10G Fibre  
Channel line cards  
Synchronous Ethernet  
Optical modules  
Wireless repeaters/  
wireless backhaul  
Data converter clocking  
xDSL  
PDH clock synthesis  
Test and measurement  
Broadcast video  
Pin Assignments  
36 35 34 33 32 31 30 29 28  
RST  
NC  
1
2
3
4
5
6
7
8
9
27 SDI  
26  
A2_SS  
25 A1  
INT_LOS1  
LOS2  
VDD  
24  
23  
A0  
GND  
Pad  
Description  
SDA_SDO  
XA  
22 SCL  
XB  
21  
20  
CKSEL  
NC  
The Si5327 is a jitter-attenuating precision clock multiplier for applications  
requiring sub 1 ps jitter performance. The Si5327 accepts two input clocks ranging  
from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz to  
808 MHz. The two outputs are divided down separately from a common source.  
The Si5327 can also use its crystal oscillator as a clock source for frequency  
synthesis. The device provides virtually any frequency translation combination  
across this operating range. The Si5327 input clock frequency and clock  
multiplication ratio are programmable through an I2C or SPI interface. The Si5327  
is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which  
provides frequency synthesis and jitter attenuation in a highly integrated PLL  
solution that eliminates the need for external VCXO and loop filter components.  
The DSPLL loop bandwidth is digitally programmable, providing jitter performance  
optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V  
supply, the Si5327 is ideal for providing clock multiplication and jitter attenuation in  
high performance timing applications.  
GND  
NC  
19 NC  
10 11 12 13 14 15 16 17 18  
Rev. 1.0 1/13  
Copyright © 2013 by Silicon Laboratories  
Si5327  

SI5327B-C-GM 替代型号

型号 品牌 替代类型 描述 数据表
SI5327D-C-GM SILICON

完全替代

Processor Specific Clock Generator, 243MHz, CMOS, QFN-36
SI5327B-C-GMR SILICON

完全替代

Processor Specific Clock Generator, 808MHz, CMOS, QFN-36

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